Sohiful Anuar MURAD ZAINOL, Izatul Syafina ISHAK, Mohd Fairus AHMAD, Shaiful Nizam MOHYAR

Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications

This paper proposes a design of a low-power operational amplifier (op-amp) for pipeline analog-to-digital converter (ADC) applications using a 0.13-µm CMOS process. The folded-cascode topology with NMOS input types is employed for the op-amp design due to a larger output gain compared to PMOS input types. Furthermore, the op-amp is designed with a double detection structure of a common-mode feedback circuit to provide stable feedback voltage. The simulation results show that the proposed op-amp achieved a gain of 64.5 dB and a unity gain bandwidth of 695.1 MHz with a low power consumption of 0.14 mW. In addition, by applying ±1.2 V of input voltage, the output voltage generated by the proposed op-amp design remains at 1.2 V with a constant feedback voltage of 1.3 V. Moreover, the proposed circuit was implemented and simulated successfully in a 1.5-bit per stage pipeline ADC.

PDF

___

[1] Anundson K, Crasso A, Thet KZ. Pipeline ADC with a nonlinear gain stage and digital correction. BSc, Worcester, MA, USA: Worcester Polytechnic Institute, 2011.
[2] Ahmed I. Pipelined ADC Design and Enhancement Techniques. Dordrecht, the Netherlands: Springer, 2010.
[3] Vatanjou A, Dadashi A, Sobhi J, Koozehkanani ZD. A high speed power efficient pipeline ADC in 0.18µm CMOS. In: IEEE 2013 Faible Tension Faible Consommation Conference; 2021 June 2013; Paris, France. New York, NY, USA: IEEE. pp. 1-4.
[4] Razavi B. Design of Analog CMOS Integrated Circuits. International Edition. New York, NY, USA: McGraw-Hill, 2001.
[5] Kant S, Sahu OP. Design of low voltage high speed operational amplifier for pipelined ADC in 90nm standard CMOS process. International Journal of Engineering Research and Technology 2012; 1: 1-5.
[6] Kun Z, Di W, Zhangfa L. A high-performance folded cascode amplifier. In: 2012 International Conference on Computer and Automation Engineering Conference; 15 January 2012; Mumbai, India. pp. 41-44.
[7] Ishak IS, Murad SAZ, Ahmad MF. Low power folded cascode CMOS operational amplifier with common mode feedback for pipeline ADC. In: 2014 International Integrated Engineering Summit Conference; 14 December 2014; Johor, Malaysia. pp. 1-4.
[8] Weixun Y, Zimmermann H. Continuous-time common-mode feedback circuit for applications with large output swing and high output impedance. In: IEEE 2008 Workshop on Design and Diagnostics of Electronic Circuits and Systems Conference; 1618 April 2008; Bratislava, Slovakia. New York, NY, USA: IEEE. pp. 1-5.
[9] Gray PR, Hurst PJ, Lewis SH, Meyer RG. Analysis and Design of Analog Integrated Circuits. 5th ed. Berkeley, CA, USA: John Wiley & Sons, 2010.
[10] Zhang MM, Hurst PJ. Effect of non-linearity in the CMFB circuit that uses the differential-difference amplifier. In: IEEE 2006 International Symposium on Circuits and Systems Conference; 2124 May 2006; Kos, Greece. New York, NY, USA: IEEE. pp. 1393-1396.
[11] Ahmad MF, Murad SAZ, Shahimin MM, Rais SAA, Hasan AF. Modified. CMFB circuit with enhanced accuracy for data converter application. Appl Mech Mater 2014; 446-447: 992-996.
[12] Hati MK, Bhattacharyya TK. Design of low power, high speed complementary input folded cascode OTA for a parallel pipeline ADC. In: IEEE 2011 Computer Society Annual Symposium on VLSI Conference; 46 July 2011; Madras, India. New York, NY, USA: IEEE. pp. 114-119.
[13] Rahim SAE, Azmi IM. A CMOS single stage fully differential folded cascode amplifier employing gain boosting technique. In: 2011 13th International Symposium on Integrated Circuits Conference; 1214 December 2011; Singapore. New York, NY, USA: IEEE. pp. 234-237.
[14] Liu X, McDonald JF. Design of single-stage folded cascode gain boost amplifier for 14 bit 12.5 Ms/S pipelined analog-to-digital converter. In: IEEE 2012 International Semiconductor Electronic Conference; 1921 September 2012; Kuala Lumpur, Malaysia. New York, NY, USA: IEEE. pp. 622-626.
[15] Ghaderi N, Hadidi K, Barani B. A novel MDAC suitable for a 14B 120 Ms/s ADC using a new folded cascode op-amp. Electrical and Electronics Engineering 2014; 3: 121-130.
[16] Mostafa C, Hiaham A, Hassan Q. Design of a low power, high speed analog to digital pipelined converter for high speed camera cmos using 0.18-µm CMOS technology. Australian Journal of Basic and Applied Sciences 2015; 9: 224-231.