Ching-Che CHUNG, Chien-Ying YU

An area-efficient and wide-range digital DLL for per-pin deskew applications

In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A test chip of the 0.042 mm2 DLL and the 3-ps-adjustable-resolution phase shifters with a 0.0025 mm2 per-channel area was implemented using a 90-nm CMOS process. Simulation results show that the phase error of the 90 ◦ phase shifter at 1.6 GHz is 2.4 ◦ . The DLL and the phase shifter consume 3.4 mW and 0.31 mW, respectively, at 1.6 GHz.

PDF

___

[1] Kim C, Lee HW, Song J. Memory interfaces: past, present, and future. IEEE Solid-St Circ Mag 2016; 8; 23-34.
[2] Burnham JR, Yeh GK, Sun E, Yang CKK. Design and analysis of a jitter-tolerant digital delay-locked-loop based fraction-of-clock delay line. In: IEEE International Solid-State Circuits Conference; 1519 February 2004; San Francisco, USA. New York, NY, USA: IEEE. pp. 352-353.
[3] Chung CC, Chen PL, Lee CY. An all-digital delay-locked loop for DDR SDRAM controller applications. In: International Symposium on VLSI Design, Automation and Test; 2628 April 2006; Taiwan, ROC. New York, NY, USA: IEEE. pp. 1-4.
[4] Bae JH, Seo JH, Yeo HS, Kim JW, Sim JY, Park HJ. An all-digital 90-degree phase-shift DLL with loop-embedded DCC for 1.6Gbps DDR interface. In: IEEE Custom Integrated Circuits Conference; 1619 September 2007; San Jose, CA, USA. New York, NY, USA: IEEE. pp. 373-376.
[5] Sheng D, Chung CC, Lee CY. Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. IEICE Electron Expr 2010; 7; 634-639.
[6] Kang H, Ryu L, Jung DH, Lee D, Lee W, Kim S, Choi J, Jung SO. Process variation tolerant all-digital 90 ◦ phase shift DLL for DDR3 interface. IEEE T Circuits-I 2012; 59; 2186-2196.
[7] Lee HW, Lim SB, Song J, Koo JB, Kwon DH, Kang JH, Kim Y, Choi YJ, Park K, Chung BT, Kim C. A 283.2µW 800Mb/s/pin DLL-based data self-aligner for through-silicon via (TSV) interface. In: IEEE International Solid-State Circuits Conference; 1923 February 2012; San Francisco, USA. New York, NY, USA: IEEE. pp. 48-49.
[8] Oh KI, Kim LS, Park KI, Jun YH, Kim K. Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface. Electron Lett 2008; 44; 1121-1123.
[9] Chen CC, Chang JY, Liu SI. A DLL-based variable-phase clock buffer. IEEE T Circuits-II 2007; 54; 1072-1076.
[10] Lee D, Kim J. 5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory. Electron Lett 2015; 51; 1973-1975.
[11] Chae JH, Hong GM, Park J, Kim M, Ko H, Shin WY, Chi H, Jeong DK, Kim S. A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180 ◦ phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. In: IEEE Asian Solid-State Circuits Conference; 911 November 2015; Xiamen, China. New York, NY, USA: IEEE. pp. 1-4.
[12] Wang JS, Cheng CY, Chou PY, Yang TY. A wide-range, low-power, all-digital delay-locked loop with cyclic halfdelay-line architecture. IEEE J Solid-St Circ 2015; 50; 2635-2644.
[13] Jung DH, Ryu K, Park JH, Jung SO. All-digital 90 ◦ phase-shift DLL with dithering jitter suppression scheme. IEEE T VLSI Syst 2016; 24; 1015-1024.
[14] Jung DH, An YJ, Ryu K, Park JH, Jung SO. All-digital fast-locking delay-locked loop using a cyclic-locking loop for DRAM. IEEE T Circuits-II 2015; 62; 1023-1027.
[15] Fujimura Y, Takahashi T, Toyoshima S, Nagashima K, Baba J, Matsumoto T. 1.2Gbps/pin simultaneous bidirectional transceiver logic with bit deskew technique. In: IEEE Symposia on VLSI Technology and Circuits Conference; 1113 June 2002; Honolulu, HI, USA. New York, NY, USA: IEEE. pp. 58-59.
[16] Hu A, Yuan F. Intersignal timing skew compensation of parallel links with voltage-mode incremental signaling. IEEE T Circuits-I 2009; 56; 773-783.
[17] Yang RJ, Liu SI. A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm. IEEE J Solid-St Circ 2007; 42; 361-372.
[18] Combes M, Dioury K, Greiner A. A portable clock multiplier generator using digital CMOS standard cells. IEEE J Solid-St Circ 1996; 31; 958-965.
[19] Hsu HJ, Tu CC, Huang SY. A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory. In: International Symposium on VLSI Design, Automation and Test; 2325 April 2008; Taiwan, ROC. New York, NY, USA: IEEE. pp. 267-270.