Umer Farooq AHMED, Muhammad Mansoor AHMED

An analytical model to assess DC characteristics of independent gate Si FinFETs

In this paper, Poisson’s equation is utilized to find the potential distribution inside the channel of anindependent gate FinFET device by adding the effect of channel height. The channel height of the device plays animportant role in surface potential calculation when top gate voltage is applied. Using surface potential, an I −V modelis developed, which can find the device current both in linear and saturation regions of operation. The model is tested ondevices of different dimensions and good agreement between modeled and simulated results is observed, which validatesthe authenticity of the proposed model.

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[1] Ananthan H, Roy K. Technology and circuit design considerations in quasi-planar double-gate SRAM. IEEE T Electron Devices 2006; 53: 242-250.
[2] Chen MC, Li KS, Li LJ, Lu AY, Li MY, Chang YH, Lin CH, Chen YJ, Hou YF, Chen CC et al. TMD FinFET with 4 nm thin body and back gate control for future low power technology. In: 2015 IEEE International Electron Devices Meeting; Washington, DC, USA; 2015. pp. 32.2.1-32.2.4.
[3] Moroz V, Smith SL, Lu Q. FinFET with Heterojunction and Improved Channel Control. Google Patents 2016.
[4] Fried DM, Duster JS, Kornegay KT. High-performance p-type independent-gate FinFETs. IEEE Electron Device Lett 2004; 25: 199-201.
[5] Yang IY, Vieri C, Chandrakasan A, Antoniadis DA. Back-gated CMOS on SOIAS for dynamic threshold voltage control. IEEE T Electron Devices 1997; 44: 822-831.
[6] Liu YX, Masahara M, Ishii K, Tsutsumi T, Sekigawa T, Takashima H, Yamauchi H, Suzuki E. Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel. In: 2003 IEEE International Electron Devices Meeting; Washington, DC, USA; 2003. pp. 18.8.1-18.8.3.
[7] Zhang W, Fossum JG, Mathew L, Du Y. Physical insights regarding design and performance of independent-gate FinFETs. IEEE T Electron Devices 2005; 52: 2198-2206.
[8] Masahara M, Endo K, Liu YX, O’uchi S, Matsukawa T, Surdeanu R, Witters L, Doornbos G, Nguyen VH, Van den bosch G et al. Four-terminal FinFET device technology. In: 2007 IEEE International Conference on Integrated Circuit Design and Technology; Austin, TX, USA; 2007. pp. 1-4.
[9] Kaur N, Rattan M, Gill SS. Impact of gate oxide thickness and aspect ratio of fin height and fin width on nanoscale tapered FinFETs. In: 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology; Bengaluru, India; 2016. pp. 1787-1791.
[10] Nowak EJ, Aller I, Ludwig T, Kim K, Joshi RV, Chuang C, Bernstein K, Puri R. Turning silicon on its edge double gate CMOS/FinFET technology. IEEE Circuits Devices Mag 2004; 20: 20-31.
[11] Tawfik SA, Liu Z, Kursun V. Independent-gate and tied-gate FinFET SRAM circuits: design guidelines for reduced area and enhanced stability. In: International Conference on Microelectronics; Cairo, Egypt; 2007. pp. 171-174.
[12] Endo K, O’uchi SI, Ishikawa Y, Liu Y, Matsukawa T, Sakamoto K, Tsukada J, Ishii K, Yamauchi H, Suzuki E et al. Enhancing SRAM cell performance by using independent double-gate FinFET. In: 2008 IEEE International Electron Devices Meeting; San Francisco, CA, USA; 2008. pp. 1-4.
[13] Guo Z, Balasubramanian S, Zlatanovici R, King TJ, Nikolić B. FinFET-based SRAM design. In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design; San Diego, CA, USA; 2005. pp. 2-7.
[14] Ni H, Hu J, Yang H, Zhu H. Comprehensive optimization of dual threshold independent-gate FinFET and SRAM cells. Active and Passive Electronic Components 2018; 2018: 4512924.
[15] Lu DD, Dunga MV, Lin CH, Niknejad AM, Hu C. A multi-gate MOSFET compact model featuring independent gate operation. In: 2007 IEEE International Electron Devices Meeting; Washington, DC, USA; 2007. pp. 565-568.
[16] Hasan M, Gaillardon PE, Sensale-Rodriguez B. A continuous compact DC model for dual-independent-gate FinFETs. IEEE J Electron Devi 2017; 5: 23-31.
[17] Datta A, Goel A, Cakici RT, Mahmoodi H, Lekshmanan D, Roy K. Modeling and circuit synthesis for independently controlled double gate FinFET devices. IEEE T Comput Aid D 2007; 26: 1957-1966.
[18] Gupta SK, Kulkarni JP, Roy K. Tri-mode independent gate FinFET-based SRAM with pass-gate feedback: technology-circuit co-design for enhanced cell stability. IEEE T Electron Devices 2013; 60: 3696-3704.