Microelectronic interconnect modeling with a periodical lumped RLC-network

A modeling of high-speed microelectronic interconnections based on periodical resistor-inductor-capacitor (RLC) cells is presented in this paper. A theoretical investigation enabling one to determine the interconnect structure transfer function is established. The proposed theory is based on the use of the ABCD matrix product of elementary cells, constituting the whole interconnect structure. After extracting the constituting lumped elements R, L, and C, which model the considered interconnection, examples of the numerical validations were proposed, both in the frequency and time domains. It was demonstrated that by considering a structure comprised of 10 elementary segments in cascade, S-parameters and time-domain results were perfectly well correlated with the microstrip interconnection electromagnetic/circuit cosimulations performed with SPICE. It was verified that by considering input square wave data with several Gigasymbols/s rates, the introduced method enables the achieving of relative errors lower than 1% when the number of used cells is higher than 10. In addition, the sensitivity of the model in the function of the interconnect line length is investigated. The proposed model permits one to accurately predict the behavior of radio frequency/microelectronic interconnection responses for different signal integrity parameters of the interconnection line load values.

Anahtar Kelimeler:

Discrete modeling method, high-speed interconnections, microelectronic application, RLC-model, signal integrity

Microelectronic interconnect modeling with a periodical lumped RLC-network

Keywords:

Discrete modeling method, high-speed interconnections, microelectronic application, RLC-model, signal integrity,

PDF

___

J. Ju, “Wide-bandwidth video switch/matrix drivers and transmission technology in consumer electronics: a new transmission scheme for digital video signals paired with current transfer logic (CTL[TM]) will help meet the market requirement for multiple display needs (analog video applications)”, IEEE Wireless Design Magazine, pp. 28–30, 200 J.J. Wells, “Faster than ﬁber: the future of multi-Gb/s wireless”, IEEE Microwave Magazine, Vol. 10, pp. 104–112, 200 International Technology Roadmap for Seminconductors (ITRS) Update Overview. http://www.itrs.net/Links/2010ITRS/Home2010.htm.
A. Allan, “Overall roadmap technology characteristics”, ITRS Winter Conference, 2007.
Y. Tomita, M. Kibune, J. Ogawa, W.W. Walker, H. Tamura, T. Kuroda, “A 10 Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11 μ m CMOS”, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 202–205, 2004.
M. Voutilainen, M. Rouvala, P. Kotiranta, T. von Rauner, “Multi-Gigabit serial link emissions and mobile terminal antenna interference”, Proceedings of the 13th IEEE Workshop on Signal Propagation on Interconnects, pp. 1–4, 200 W. Maichen, “When digital becomes analog - interfaces in high speed test”, Proceedings of the IEEE VLSI Test Symposium, pp. 0–22, 2008.
J. Zhang, T.Y. Hsiang, “Extraction of subterahertz transmission-line parameters of coplanar waveguides”, PIERS Online, Vol. 3, pp. 1102–1106, 2007.
K.O. Kenneth, “Aﬀordable terahertz electronics”, IEEE Microwave Magazine, Vol. 10, pp. 113–116, 2009.
J.L. Wyatt Jr, Q. Yu, “Signal delay in RC meshes, trees and lines”, Proceedings of the IEEE International Conference on Auditory Display, pp. 15–17, 1984.
Y.I. Ismail, E.G. Friedman, J.L. Neves, “Equivalent Elmore delay for RLC trees”, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 19, pp. 83–97, 2000.
X.C. Li, J.F. Mao, M. Tang, “High-speed clock tree simulation method based on moment matching”, Progress in Electromagnetics Research Symposium, pp. 178–181, 2005.
V. Champac, V. Avendano, J. Figueras, “Built-in sensor for signal integrity faults in digital interconnect signals”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, pp. 256–269, 2010.
A. Nieuwoudt, J. Kawa, Y. Massoud, “Crosstalk-induced delay, noise, and interconnect planarization implications of ﬁll metal in nanoscale process technology”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, pp. 378–391, 2010.
A.K. Palit, V. Meyer, K.K. Duganapalli, W. Anheier, J. Schloeﬀel, “Test pattern generation based on predicted signal integrity loss through reduced order interconnect model”, Proceedings of the 16th Workshop Test Methods and Reliability of Circuits and Systems, pp. 84–88, 2004.
A.C. Scogna, A. Orlandi, V. Ricciuti, “Signal and power integrity performances of striplines in presence of 2D EBG planes”, Proceedings of the 12th IEEE Workshop on Signal Propagation on Interconnects, pp. 1–4, 2008.
A. Deutsch, G.V. Kopcsay, V.A. Ranieri, J.K. Cataldo, E.A. Galligan, W.S. Graham, R.P. McGouey, S.L. Nunes, J.R. Paraszczak, J.J. Ritsko, R.J. Serino, D.Y. Shih, J.S. Wilczynski, “High-speed signal propagation on lossy transmission lines”, IBM Journal of Research and Development, Vol. 34, pp. 601–615, 1990.
F. Schnieder, W. Heinrich, “Model of thin-ﬁlm microstrip line for circuit design”, IEEE Transactions on Microwave Theory and Techniques, Vol. 49, pp. 104–110, 2001.
J. Cong, L. He, C.K. Koh, P.H. Madden, “Performance optimization of VLSI interconnect layout”, Integration, the VLSI Journal, Vol. 21, pp. 1–94, 1996.
M. Qungang, Y. Yintang, L. Yuejin, J. Xinzhang, “Optimal cascade lumped model of deep submicron on-chip interconnect with distributed parameters”, Microelectronic Engineering, Vol. 77, pp. 310–318, 2005.
W.C. Elmore, “The transient response of damped linear networks with particular regard to wideband ampliﬁers”, Journal of Applied Physics, Vol. 19, pp. 55–63, 1948.
L. Wyatt, Circuit Analysis, Simulation and Design, Amsterdam, Elsevier Science, 1978.
A.B. Kahng, S. Muddu, “An analytical delay model of RLC interconnects”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, pp. 1507–1514, 1997.
A. Ligocka, W. Bandurski, “Eﬀect of inductance on interconnect propagation delay in VLSI circuits”, Proceedings of the 8th IEEE Workshop on Signal Propagation on Interconnects, pp. 121–124, 2004.
V. Adler, E.G. Friedman, “Repeater design to reduce delay and power in resistive interconnect”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, pp. 607–616, 1998.
Y.I. Ismail, E.G. Friedman, “Eﬀects of inductance on the propagation, delay and repeater insertion in VLSI circuits”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 8, pp. 195–206, 2000.
B. Ravelo, A. Perennec, M. Le Roy, “A new technique of interconnect eﬀects equalization by using negative group delay active circuits”, VLSI Intech Book, pp. 409–434, 2010.
B. Ravelo, A. Perennec, M. Le Roy, “Equalization of interconnect propagation delay with negative group delay active circuits”, Proceedings of the 11th IEEE Workshop on Signal Propagation on Interconnects, pp. 15–18, 2007. B. Ravelo, A. Perennec, M. Le Roy, “Application of negative group delay active circuits to reduce the 50% propagation delay of RC-line model”, Proceedings of the 12th IEEE Workshop on Signal Propagation on Interconnects, pp. 1–4, 2008.
B. Ravelo, A. Perennec, M. Le Roy, “Experimental validation of the RC-interconnect eﬀect equalization with negative group delay active circuit in planar hybrid technology”, Proceedings of the 13th IEEE Workshop on Signal Propagation on Interconnects, pp. 1–4, 2009.
T. Eudes, B. Ravelo, A. Louis, “Transient response characterization of the high-speed interconnection RLCG-model for the signal integrity analysis”, Progress in Electromagnetics Research, Vol. 112, pp. 183–197, 2011.
B. Ravelo, T. Eudes, “Fast estimation of RL-loaded millimetre interconnection delay for the signal integrity prediction”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 25, pp. 338–346, 2012.