Sunghoon SHIM, Sungwoo CHUNG, Hongjun CHOI, Cheol Hong KIM

Early wakeup: improving the drowsy cache performance

As process technology scales down, leakage power consumption becomes comparable to dynamic power consumption. The drowsy cache technique is known as one of the most popular techniques for reducing the leakage power consumption in the data cache. However, the drowsy cache is reported to degrade the processor performance significantly. In this paper, to maintain the performance of the processor with the drowsy cache technique, we propose an early wakeup technique, which predicts the next cache line to be requested by utilizing the way-prediction information. The proposed technique efficiently reduces the number of accesses to the cache lines in drowsy mode. Our simulation results show that the proposed technique reduces the extra delay due to the drowsy cache scheme by 29.6%, on average.

Anahtar Kelimeler:

Processor architecture, low-power design, leakage power, drowsy cache, early wakeup

Early wakeup: improving the drowsy cache performance

Keywords:

Processor architecture, low-power design, leakage power, drowsy cache, early wakeup,

PDF

___

M. Powell, S.H. Yang, B. Falsafi, K. Roy, T.N. Vijaykumar, “Gated-V dd : a circuit technique to reduce leakage in deep-submicron cache memories”, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 90–95, 2000.
S. Kaxiras, Z. Hu, M. Martonosi, “Cache decay: exploiting generational behavior to reduce leakage power”, Proceedings of the International Symposium on Computer Architecture, pp. 240–251, 2001.
K. Flautner, N.S. Kim, S. Martin, D. Blaauw, T. Mudge, “Drowsy caches: simple techniques for reducing leakage power”, Proceedings of the International Symposium on Computer Architecture, pp. 148–157, 2002.
R. Giorgi, P. Bennati, “Filtering drowsy instruction cache to achieve better efficiency”, Proceedings of the ACM Symposium on Applied Computing, pp. 1554–1555, 2008.
S. Petit, J. Sahuquillo, J.M. Such, D. Kaeli, “Exploiting temporal locality in drowsy cache policies”, Proceedings of the 2nd Conference on Computing Frontiers, pp. 371–377, 2005.
S.W. Chung, K. Skadron, “On-demand solution to minimize I-cache leakage energy with maintaining performance”, IEEE Transactions on Computers, Vol. 57, pp. 7–24, 2008.
M.B.C. Alioto, P. Bennati, R. Giorgi, “Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed”, Proceedings of the International Symposium on Circuits and Systems, pp. 37–40, 2010. S.H. Shim, C.H. Kim, J.W. Kwak, C.S. Jhon, “Hybrid technique for reducing energy consumption in high performance embedded processor”, Proceedings of the International Conference on Embedded and Ubiquitous Computing, Vol. 3207, pp. 74–84, 2004.
M.D. Powell, A. Agarwal, T.N. Vijaykumar, B. Falsafi, K. Roy, “Reducing set-associative cache power via wayprediction and selective direct-mapping”, Proceedings of the International Symposium on Microarchitecture, pp. 54–65, 2001.
B. Batson, T.N. Vijaykumar, “Reactive associative caches”, Proceedings of the International Conference on Parallel Architectures and Compilation, 2001.
ARM Co., ARM Technical Reference Manual, available at http://infocenter.arm.com/help/index.jsp. T.R. Halfhill, “Intel’s tiny ATOM: new low-power microarchitecture rejuvenates the embedded x86”, Microprocessor Report, Vol. 22, pp. 1–16, 2008.
M.E. Thomadakis, “The architecture of the Nehalem processor and Nehalem-EP SMP platforms”, Research Report, Texas A&M University, 2011.
K. Diefendorff, “K7 challenges Intel: new AMD processor could beat Intel’s Katmai”, Microprocessor Report, Vol. 12, pp. 1–7, 1998.
N.S. Kim, K. Flautner, D. Blaauw, T. Mudge, “Single-V dd and single-V T super-drowsy techniques for low-leakage high-performance instruction caches”, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 54–57, 2004.
D. Brooks, V. Tiwari, M. Martonosi, “Wattch: a framework for architectural-level power analysis and optimizations”, Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 83–94, 2000. D. Nicolaescu, A. Veidenbaum, A. Nicolau, “Reducing data cache energy consumption via cached load/store queue”, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 252–257, 2003.