A data-aware write-assist 10T SRAM cell with bit-interleaving capability

Cell stability is becoming an important design concern as process technology continues to scale down. In thispaper, we present a single-ended 10T SRAM cell that improves simultaneously both read static noise margin (RSNM)and write static noise margin (WSNM) by employing separate read buffer and power gating transistors, respectively. Thecross-point write structure of the proposed cell facilitates bit-interleaved architecture to enhance soft-error immunity.Simulation is done on 65-nm CMOS technology on Cadence. Simulation results show that the RSNM of the proposedSRAM cell is 2.78 times and 1.47 times higher than those of the conventional 6T and Schmitt trigger-based 10T (ST-2)cells, respectively, at 0.4 V. The WSNM of the proposed design is 5.14 times larger than that of the two-port disturbfree 9T (TPDF9T) cell (without write assist) at 0.4 V. Write delay of the proposed cell is 77.56% less than that of theTPDF9T cell at 0.4 V. Leakage power dissipation of the proposed SRAM cell is 0.89 times that of the ST-2 cell at0.4 V. The proposed cell occupies 1.34 times more area than the conventional 6T cell

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