Suresh ALAPATI, Sreehari Rao PATRI

Improved transient response capacitor less low dropout regulator employing adaptive bias and bulk modulation

This paper presents a low quiescent current, fast settling time, and adaptively biased capacitor less lowdropout (LDO) regulator. The topology involves a segmented pass transistor with bulk modulation and adaptivelybiased current control stages to improve the transient performance. The bulk modulation of the pass transistor assistsin fast settling of the output voltage. The frequency compensation makes the LDO voltage regulator stable adaptivelyover load current transitions. In addition, the biasing stage is designed such that it adapts to the load transitionswhile consuming the quiescent current abstemiously. This arrangement further improves settling time to be within 1 µswhile restricting undershoot/overshoot to 171 mV/82 mV for a load current transition between 0 and 100 mA with loadcapacitor of 40 pF. The LDO regulator is designed using 0.18 µm UMC CMOS process by consuming 1.5 µA quiescentcurrent at no loads

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