Veerana SUBBIAH, Prabhakaran DEEPA, Nallathambi RAMYARANI

Design of area-efficient IIR filter using FPPE

Floating point arithmetic circuits provide wide dynamic range and high precision, and they are widely usedin scientific computing and signal processing applications, but the complexity increases in hardware implementationsof floating point units. In VLSI design architecture, many applications suffer in size of the components used in logicaloperations. The aim of reducing architecture is to gain reduction in power loss and also in area, but the reduction insize of the components leads to an increase in delay and memory. Hence, to overcome these limitations and to optimizethe area, a novel design of floating point processing element (FPPE) architecture is proposed in this work with a smallernumber of logical components and registers. A partially folded arithmetic function architecture is modeled for the designof an infinite impulse response (IIR) filter using FPPE and implemented on a field programmable gate array (FPGA)with efficient area. FPGAs are widely used in the implementation of floating point computing modules due to theincrease in gate density and embedded arithmetic cores. Synthesis results prove that the proposed design of the IIR filterprovides efficient area compared with existing works. The modules are designed in Verilog and implemented on XilinxFPGAs.

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