Accurate Prediction of Crosstalk for RC Interconnects

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RC lines for use in design automation tools. The method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveform. Noise peak and width expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is 4.1% and for the width is 6.8% while allowing for very fast analysis.

Accurate Prediction of Crosstalk for RC Interconnects

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RC lines for use in design automation tools. The method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveform. Noise peak and width expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is 4.1% and for the width is 6.8% while allowing for very fast analysis.

___

  • A. Vittal and M. Marek-Sadowska. “Crosstalk reduction for VLSI”, IEEE Transactions on Computer-Aided Design, Vol. 16, pp. 1817-24, 1997.
  • A. B. Kahng, S. Muddu, and D. Vidhani, “Noise and delay uncertainty studies for coupled RC interconnections”, IEEE Int. ASIC/SOC Conf., pp. 3-8, 1999.
  • S. Nakagawa, D. M. Sylvester, J. McBride, and S.-Y.Oh “On-chip crosstalk noise model for deep submicrometer ULSI interconnect”, H. P. Journal, Vol. 49, pp.39-45, 1998.
  • J. Cong, D.Z. Pan, and P. V. Srinavas, “Improved crosstalk modeling for noise constrained interconnect optimiza- tion”, Proceedings of ASP/DAC, pp. 373-378, 2001.
  • M. R. Becer, D. Blaauw, V. Zolotov, R. Panda, I. N. Hajj, ”Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model”, 2002 Design, Automation and Test in Europe Conference, pp. 456-464, 2002.
  • T. Sato, Y. Cao, K. Agarwal, D. Sylvester, and C. Hu, ”Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay change curves,” IEEE Transactions on Computer-Aided Design, vol. 22, no. 5, pp. 560-572, 2003.
  • K. Agarwal, Y. Cao, T. Sato, D. Sylvester, and C. Hu, ”Efficient generation of delay change curves for noise-aware static timing analysis” Proc. of Asia and South Pac. Design Automation Conf., pp. 77-84, 2002.
  • M. Kuhlmann, S. S. Sapatnekar, K. K. Parhi, “Efficient crosstalk estimation”, International Conference on Com- puter Design (ICCD ’99), pp. 266 – 272, 1999.
  • R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav, S. Sirichotiyakul, and V. Zolotov, “Clarinet: A noise analysis tool for deep submicron design”, in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 587-594.
  • J. Qian, S. Pullela, and L. T. Pillage, “Modeling the effective capa- citance for the RC interconnect of CMOS gates,” IEEE Transactions on Computer-Aided Design, Vol. 13, pp. 1526–1535, 1994.
  • L. T. Pillage and R. A. Rohrer, “Asymptotic Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 4, pp. 352 - 366, 1990.
  • E. Acar, A. Odabasioglu, M. Celik, and L. Pileggi. “S2p: a stable 2- pole RC delay and coupling noise metric IC interconnects”, Proceedings 9th Great Lakes Symposium on VLSI, pp 60-63, 1999.