A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder

This paper presents a 5-bit flash analog-to-digital converter design using the 0.18-m m Taiwan Semiconductor Manufacturing Company's CMOS technology library. The designed system consists of 2 main blocks, a comparator array, and a digital decoder. The digital decoder contains a latch, 1-of-N decoder, and fat-tree encoder units. The 1-of-N decoder is implemented using 2 \times 1 multiplexers. As a result, the active die area and the power consumption are reduced, in addition to an increase in the sampling frequency. The power supply voltage range for the overall system is \pm 0.9 V. For testing purposes, a ramp signal of between --0.45 V and 0.7 V is applied to the converter input. The sampling frequency is 5 Gs/s. The simulation results include a maximum power consumption of 28 mW, integral nonlinearity values of between --0.65 least significant bits (LSB) and +0.01 LSB, differential nonlinearity values of between --0.3 LSB and +0.13 LSB, and an active die area of 0.1 mm2.

Anahtar Kelimeler:

Flash ADC, CMOS VLSI, high-speed data converters

A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder

Keywords:

Flash ADC, CMOS VLSI, high-speed data converters,

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Proposed Technology (CMOS) 0.18 µm 0.13 µm 0.18 µm 65 nm 0.18 µm Resolution 5-bit 5-bit 4-bit 5-bit 5-bit Power supply voltage ±0.9 V 2 V 8 V 3 V and 1 V 8 Power (mW) 28 120 80 1 36 Analog input range –0.45 V to 0.7 V 0.8 V pp – 0.8 V pp 1 V pp Sampling frequency (Gs/s) 5 2 0.7 5 056 Max INL (LSB) –0.65 13 0.27 0.33 0.56 Max DNL (LSB) –0.3 12 0.19 –0.3 0.32 Calibration No Yes Yes Yes No Active chip area (mm 2 ) 0.1 0.18 – 0.035 – results, the 2 × 1 Mux-based decoder structure improves the performance in terms of the speed and power consumption. Moreover, it is also thought that the proposed ADC architecture is attractive for designers from a design complexity point of view. The layout photo of the complete converter is shown in Figure 16. As a future work, the performance of the proposed 1-of-N decoder structure will be compared to alternative types of 1-of-N decoder performances. In addition, further improvements are planned in the encoder architecture. Figure 16. The layout photo of the complete converter. Acknowledgment This study was financially supported by the Kocaeli University Scientific Research Division under Project Number BAP-2009/40 (Microelectronic Laboratory). References O. Aytar, “Katlamalı ve arade˘ gerlemeli analog-sayısal d¨ on¨ ust¨ ur¨ uc¨ ulerin VLSI tasarımında e¸sik evirmeli nicemleyici tekni˘ gi’nin kullanımı ve performansı”, PhD, Kocaeli University, ˙Izmit, Turkey, 2009. C.C. Chen, Y.L. Chung, C.I. Chiu, “6-b 1.6GS/s flash ADC with distributed track-and-hold pre-comparators in a 0.18 µ m CMOS”, International Symposium on Signals, Circuits and Systems, pp. 1–4, 2009. L. Wu, F. Huang, Y. Gao, Y. Wang, J. Cheng, “42 mW 2 GS/s 4-bit flash ADC in 0.18 µ m CMOS”, International Conference on Wireless Communications & Signal Processing, pp. 1–5, 2009. Y.Z. Lin, C.W. Lin, S.J. Chang, “5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, pp. 509–513, 2010. S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18 µ m CMOS”, IEEE International Symposium on Circuits and Systems, pp. 6138–6141, 2005. S. Park, Y. Palaskas, M.P. Flynn, “A 4-GS/s 4-bit flash ADC in 0.18 µ m CMOS”, IEEE Journal of Solid State Circuits, Vol. 42, pp. 1865–1872, 2007. K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, M. Segami, “A 7 bit 800 Msps 120 mW folding and interpolation ADC using a mixed-averaging scheme”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 138–139, 200 C. Chen, J. Ren, “An 8-bit 200 M samples/s folding and interpolation ADC in 0.25 mm 2 ”, Analog Integrated Circuits and Signal Processing, Vol. 47, pp. 203–206, 2006. K. S ¸ahin, O. Aytar, A. Tangel, “5 Bit 2.5 Gs/s paralel (Flash) analog sayısal d¨ on¨ u¸st¨ ur¨ uc¨ u tasarımı”, ElektrikElektronik Bilgisayar Sempozyumu, pp. 125–130, 2011.
W.S. Chu, K.W. Current, “A CMOS voltage comparator with rail-to-rail input-range”, Analog Integrated Circuits and Signal Processing, Vol. 19, pp. 145–149, 1999.
E. Sail, M. Vesterbacka, “A multiplexer based decoder for flash analog-to-digital converters”, IEEE Region 10 Conference , pp. 250–253, 2004.
D. Lee, D. Yoo, K. Choi, J. Ghaznavi, “Fat tree encoder design for ultra-high speed flash A/D converters”, The 45th Midwest Symposium on Circuits and Systems, pp. 87–90, 2002.
V. Hiremath, S. Ren, “An ultra-high speed encoder for 5GSPS flash ADC”, IEEE International Instrumentation and Measurement Technology Conference, pp. 136–141, 2010.
Z. Liu, S. Jia, Y. Wang, Z. Ji, X. Zhang, “Efficient encoding scheme for folding ADC”, 9th International Conference on Solid-State and Integrated-Circuit Technology, pp. 1988–1991, 2008.
University of California Berkeley, EECS Instructional and Electronics Support, http://inst.eecs.berkeley.edu/ ∼n247/matlab files/inldnl.m, accessed 6 December 2011.
G. Torfs, Z. Li, J. Bauwelinck, X. Yin, G. van der Plas, J. Vandewege, “Low-power 4-bit flash analogue to digital converter for ranging applications”, Electronics Letters, Vol. 47, pp. 20–22, 2011.
W.H. Ma, J.C. Kao, M. Papaefthymiou, “A 5.5 GS/s 28 mW 5-bit flash ADC with resonant clock distribution”, Proceedings of the 37th European Solid-State Circuits Conference, pp. 155–158, 2011.
J.X. Ma, S.W. Sin, S.P. U, R.P Martins, “A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications”, International Symposium on Circuits and Systems, pp. 4305–4308, 2006.