Prabaharan NATARAJAN, Palanisamy K

Investigation of single phase reduced switch count asymmetric multilevel inverter using advanced pulse width modulation technique

In this paper, a new topology for Multilevel Inverter (MLI) with reduced switch count is proposed with an asymmetric dc source configuration. This configuration is used to double the output voltage level in multilevel inverter based on switched dc sources, by adding two switches with dc sources. The increased number of levels in the output voltage reduces the filtering requirements. The working principle of the proposed asymmetric inverter is presented through the single phase fifteen level inverter. The harmonic contents of different modulation indices are examined. The performance analysis of the inverter is compared with trapezoidal and Sinusoidal Pulse Width Modulation (SPWM) in terms of Total Harmonic Distortion (THD), fundamental rms voltage (Vrms) and Crest Factor (CF). The simulation results for the same are evaluated using MATLAB/SIMULINK

Keywords:

Asymmetric; crest factor; multilevel inverter; pulse width modulation; total harmonic distortion,

PDF

___

J. Rodríguez and J. Lai, “Multilevel Inverters: A Survey of Topologies, Controls, and Applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, 2002.
K. K. Gupta and S. Jain, “A multilevel Voltage Source Inverter (VSI) to maximize the number of levels in output waveform,” Int. J. Electr. Power Energy Syst., vol. 44, pp. 25–36, 2013.
K. K. Gupta and S. Jain, “Topology for multilevel inverters to attain maximum number of levels from given DC sources,” IET Power Electron., vol. 5, no. 4, p. 435, 2012.
S. Jain and K. K. Gupta, “Multilevel inverter topology based on series connected switched sources,” IET Power Electron., vol. 6, no. 1, pp. 164–174, Jan. 2013.
K. K. Gupta and S. Jain, “A Novel Multilevel Inverter Based on Switched DC Sources,” IEEE Trans. Ind. Electron., vol. 61, no. 7, pp. 3269–3278, 2014..
E. Babaei and M. Farhadi Kangarlu, “Cross-switched multilevel inverter: an innovative topology,” IET Power Electron., vol. 6, no. 4, pp. 642–651, Apr. 2013.
M. Sabahi, E. Babaei, and M. Farhadi Kangarlu, “Cascaded cross-switched multilevel inverter in symmetric and asymmetric conditions,” IET Power Electron., vol. 6, no. 6, pp. 1041–1050, Jul. 2013..
K. K. Gupta and S. Jain, “Comprehensive review of a recently proposed multilevel inverter,” IET Power Electron., vol. 7, no. 3, pp. 467–479, Mar. 2014.
S. Thamizharasan, S. Jeevananthan, J. Baskaran, and S. Ramkumar, “Cross-switched multilevel inverter using auxiliary reverse-connected voltage sources,” IET Power Electron., vol. 7, no. 6, pp. 1519–1526, Jun. 2014.
Y.H. Liao and C.M. Lai, “Newly-Constructed Simplified Single-Phase Multistring Multilevel Inverter Topology for Distributed Energy Resources,” IEEE Trans. Power Electron., vol. 26, no. 9, pp. 2386–2392, Sep. 2011.
S. K. Chattopadhyay and C. Chakraborty, “Multilevel Inverters with Level Doubling Network: A New Topological Variation,” 39th Annu. Conf. IEEE Ind. Electron.Soc., vol. 2, pp. 6263–6268, 2013.
S. K. Chattopadhyay and C. Chakraborty, “A New Multilevel Inverter Topology With Self-Balancing Level Doubling Network,” IEEE Trans. Ind. Electron., vol. 61, no. 9, pp. 4622–4631, 2014.
N. K. Dewangan, V. Gurjar, S. U. Ullah, and S. Zafar, “A Level-Doubling Network (LDN) for Cross- Connected Sources Based Multilevel Inverter (CCS- MLI),” IEEE Int. Conf. Power Electron. Drives Energy Syst., pp. 4–7, 2014.
S. M. Ayob, Z. Salam, and A. Jusoh, “Trapezoidal PWM Scheme for Cascaded Multilevel Inverter,” IEEE Int. Power Energy Conf., pp. 368–372, Nov. 2006.
P. Palanivel and S. S. Dash, “Analysis of THD and output voltage performance for cascaded multilevel inverter techniques,” IET Power Electron., vol. 4, no. 8, p. 951, 2011. width modulation
M.F. Kangarlu and E. Babaei, “A Generalized Cascaded Multilevel Inverter Using Series Connection of Submultilevel Inverters,” IEEE Trans. Power. Electron., vol. 28, no. 2, pp. 625–636, 2013.
M. D. Manjrekar and T. A. Lip, “A hybrid multilevel inverter topology for drive applications,” Appl. Power Electron. Conf. Expo., vol. 2, pp. 523–529, 1998.
E. Babaei and S. H. Hosseini, “Charge Balance Control Methods Converters,” Int. Conf. Electr. Mach. Syst., pp. 74–79, 2007. Cascade Multilevel
E. Babaei and S. H. Hosseini, “New cascaded multilevel inverter topology with minimum number of switches,” Energy Convers.Manag., vol. 50, no. 11, pp. 2761–2767, Nov. 2009.
E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. T. Haque, and M. Sabahi, “Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology,” Electr. Power Syst. Res., vol. 77, no. 8, pp. 1073–1085, Jun. 2007.
E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. T. Haque, and M. Sabahi, “Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology,” Electr. Power Syst. Res., vol. 77, no. 8, pp. 1073–1085, Jun. 2007.
R.S. Alishah, D. Nazarpour, S.H. Hosseini and M. Sabahi, “A new series parallel switched multilevel dc- link inverter topology,” Int. J. Electr. Power Energy Syst., vol. 36, no. 1, pp. 93–99, Mar. 2012.