Interface Effects of Annealing Temperatures in Al/HfO2/p-Si (MIS) Structures

In this study, Al/HfO2/p-Si (MIS) structures were prepared by using the sol-gel method for three different annealing temperatures.  The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of these structures were investigated by taking into consideration the effect of the interfacial insulator layer and surface states (Nss) at room temperature. All of the structures showed non-ideal I-V behaviour with ideality factor (n) in the range between 2.35 and 4.42 owing to interfacial insulator layer and surface states. The values of Nss and barrier height (fb) for three samples were calculated. The values of n and Nss ascend with increasing the insulator layer thickness (δ) while the values of fb decreases. 

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