Bahadır ÖZKILBAÇ, Tevhit KARACALI

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time in the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

Anahtar Kelimeler:

reconfigurable hardware

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

Keywords:

FPGA, ARM, RISC, Reconfigurable Hardware reconfigurable hardware,

PDF

___

Amit, S. (2006). Mac OS X internals: a systems approach. In: Addison-Wesley Professional.
Ball, J. (2007). Designing soft-core processors for FPGAs. In Processor Design (pp. 229-256): Springer.
Bhakti, T. L., Susanto, A., Santosa, P. I., & Widayati, D. T. (2012). Design of Bovine Semen Temperature Controller Using PID. Int. J. of Comp. Eng. Res, 2(7), 52-58.
Bilal, M., & Masud, S. (2007). Efficient color space conversion using custom instruction in a risc processor. Paper presented at the 2007 IEEE International Symposium on Circuits and Systems.
Chang, C.-T., Chang, C.-T., Yang, H.-L., & Chang, H.-T. (1996). Real-time implementation of speech recognition using RISC processor core. Paper presented at the Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.
Chikodi, P., & Kulkarni, M. Implementation of RISC Microprocessor for DSP Systems, 2(12), 536-540.
Electrical, I. o., Committee, E. E. C. S. S., & Stevenson, D. (1985). IEEE standard for binary floating-point arithmetic: IEEE.
Fisher, R. A. and Marshall M. 1988. “UCI repository of machine learning databases”. University of California. Available online at: https://archive.ics.uci.edu/ml/datasets/iris.
Garbey, M. (2005). Acceleration of the Schwarz method for elliptic problems. SIAM Journal on Scientific Computing, 26(6), 1871-1893.
Ghaturle, M. S., & Kadam, R. (2017). Review Paper on 32-Bit RISC Processor with Floating Point Arithmetic. Int. Research Journal of Engineering and Technology (IRJET), 4.
Hauck, S., & DeHon, A. (2010). Reconfigurable computing: the theory and practice of FPGA-based computation: Elsevier.
Kadam, S. U., & Mali, S. (2016). Design of risc processor using VHDL. 2016 International Journal of Research Granthaalaya, 4(6).
Kumar, P. S., Shashidhar, B., & Bhargav, J. S. (2010). Image acquisition from CMOS Active Pixel Sensor using RISC processor. Paper presented at the 2010 International Conference on Signal and Image Processing.
LaMeres, B. J. (2019). Introduction to logic circuits & logic design with VHDL: Springer.
Luker, J. D., & Prasad, V. B. (2001). RISC system design in an FPGA. Paper presented at the Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No. 01CH37257).
Mane, P. S., Gupta, I., & Vasantha, M. (2006). Implementation of RISC Processor on FPGA. Paper presented at the 2006 IEEE International Conference on Industrial Technology.
Mohammad, I., Ramananjaneyulu, K., & Veeraswamy, K. (2012). FPGA implementation of a 64-bit RISC processor using VHDL. International Journal of Engineering Research and Applications (IJERA), 2(3), 2544-2549.
Palekar, S., & Narkhede, N. (2016). 32-Bit RISC processor with floating point unit for DSP applications. Paper presented at the 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT).
Thakor, K. P., & Pal, A. (2017). Design of a 16-bit RISC Processor Using VHDL. Int. J. Eng. Res. Technol.(IJERT), 6.
Valli, B., Kumar, A. U., & Bhaskar, B. V. (2012). FPGA Implementation and Functional Verification of a Pipelined MIPS Processor 1.
Yamada, K., Kojima, M., Shimizu, T., Sato, F., & Mizuno, T. (2002). A new RISC processor architecture for MPEG-2 decoding. IEEE Transactions on Consumer Electronics, 48(1), 143-150.