Kim Ho YEAP, Humaira NİSAR, Veerendra DAKULAGİ

Warpage Reduction for Power MOSFET Wafers

Wafer warpage is a baseline issue faced by semiconductor manufacturers and is, in fact, particularly conspicuous among those which are involved in thefabrication of power metal oxide semiconductor field effect transistors (MOSFETs). This is because vertical MOSFETs experience larger warpage effectscompared with their conventional lateral counterparts. Wafers with warpage exceeding its critical value fail to be chucked by vacuum adsorption duringthe automatic handling process; the devices fabricated in the wafer face reliability issues as well. This paper presents an analysis on various mechanismsemployed to reduce warpage in power MOSFET wafers. The warpage behavior was examined by varying the backside metallization (BSM) thickness, thesputtering power for film deposition and the wafer’s temperature (i.e., a cryogenic condition was introduced into the process). The results suggest thatboth the BSM thickness and wafer’s temperature do not manifest a clear correlation with the wafer warpage when the front-end fabrication process iscompleted. The wafer bow level was, however, found to be in direct proportion with the magnitude of the sputtering power. When the sputtering poweris reduced, less residual stress is induced to deform the wafer structure. Hence, the sputtering power could be adjusted to ensure that the warpage effectstays below its critical value

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