FPGA Based Low Cost Automatic Test Equipment for Digital Circuits

Testing of digital circuits is a crucial problem. There are two types of Automatic Test Equipment (ATE): Very precise but complex and expensive test equipments called high-end ATE and their approximate but cheap alternatives called low-end ATE. In this paper we propose a very cheap, FPGA based embedded low-cost ATE (ELATE) that is capable of functional, speed/delay and power consumption tests. It is composed of FPGA hardware with six FSM modules written in Verilog and a computer software (user interface) communicating with the FPGA through UART. It can handle different I/O combinations and can detect delay with 4ns precision. It can both visually show the resultant voltage/current-time graphs and store them as text files. The ATE is tested on different Design Under Test (DUT) devices like 8-bit and 12-bit adders and a square root circuit implemented on FPGA.

PDF

___

IC Test Systems – Advantest (March 2018).Available: https://www.advantest.com/products/ic-test-systems.

Production Board Test Teradyne (March 2018). Available: http://www.teradyne.com/products/production-board-test.

Teseda Corporation: Silicon Failure Analysis and Yield Enhancement (March 2018). Available: http://www.teseda.com.

Teseda breaks $200 per pin ATE barrier (March 2018). Available: http://www.eetimes.com/document.asp?doc_id=1175064.

L. Mostardini, L. Bacciarelli, L. Fanucci, L. Bertini, M. Tonarelli, M. De Marinis, “FPGA-based low-cost automatic test equipment for digital integrated circuits”, IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, Rende, pp. 32-37, 2009. [CrossRef]

J. H. M. Escobar, J. SachBe, S. Ostendorff, H. D. Wuttke, “Automatic generation of an FPGA based embedded test system for printed circuit board testing”, 13th Latin American Test Workshop (LATW), Quito, Ecuador, pp. 1-6, 2012. [CrossRef]

I. Aleksejev, A. Jutman, S. Devadze, S. Odintsov, T. Wenzel, “FPGA-based synthetic instrumentation for board test,” IEEE International Test Conference, Anaheim, CA, pp. 1-10, 2012. [CrossRef]

A. A. Bayrakci, “ELATE: Embedded low cost automatic test equipment for FPGA based testing of digital circuits”, 2017 10th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, 2017, pp. 1281-1285.

F. S. Marques, R. P. Ribas, S. Sapatnekar, and A. I. Reis. “A new approach to the use of satisfiability in false path detection.” Proceedings of the 15th ACM Great Lakes symposium on VLSI (GLSVLSI ‘05). ACM, New York, NY, USA, pp 308-311, 2005. [CrossRef]

N. Eén, N. Sörensson. “An extensible SAT-solver”, International conference on theory and applications of satisfiability testing. Springer, Berlin, Heidelberg, 2003.

Documented Verilog UART (March 2018). Available: https://opencores.org/project/osdvu.