A DTMOS based Four-Quadrant Analog Multiplier

One of the most common circuit structures, four-quadrant analog multipliers (FQAM) are frequently preferred for modulation, phase shifting, adaptive filtering, neural network applications. In this study, an FQAM design is presented using dynamic threshold voltage MOSFET (DTMOS) technology. Various analyses were performed to evaluate the function of the proposed multiplier. Power consumption is limited by selecting ±0.2 V supply voltage. The power consumption of the circuit is calculated as 37 nW. The maximum amplitude of the input signal is 0.1 V. The bandwidth of the multiplier is 3.23 MHz. The total harmonic distortion (THD) of the output signal at the maximum value of the input signal and at a frequency of 100 kHz is around 1.2%. Intermodulation products were calculated to analyze the linearity of the circuit. The changes in DC and AC transfer characteristics according to temperature changes were investigated. Monte Carlo analysis was performed to verify the circuit's robustness against variation of the circuit parameters. In summary, low power consumption and THD, and insensitive of temperature variations are the outstanding features of the circuit when compared with the literature

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1. W. Liu and S. I. Liu, “Design of a CMOS low-power and low-voltage four-quadrant analog multiplier,” Analog Integr. Circuits Signal Process., vol. 63, no. 2, pp. 307–312, 2010.

2. M. M. Maryan and S. J. Azhari, “A MOS translinear cell-based configurable block for current-mode analog signal processing,” Analog Integr. Circuits Signal Process., vol. 92, no. 1, pp. 1–13, Jul. 2017.

3. M. M. Maryan, A. Ghanaatian, S. J. Azhari, and A. Abrishamifar, “Low-Power High-Speed Analog Multiplier/Divider Based on a New Current Squarer Circuit,” Arab. J. Sci. Eng., vol. 43, no. 6, pp. 2909–2918, 2018.

4. S. Menekay, R. C. Tarcan, and H. Kuntman, “Novel high-precision current-mode circuits based on the MOS-translinear principle,” AEU - Int. J. Electron. Commun., vol. 63, no. 11, pp. 992–997, 2009.

5. M. A. Al-Absi and I. A. As-Sabban, “A New Highly Accurate CMOS Current-Mode Four-Quadrant Multiplier,” Arab. J. Sci. Eng., vol. 40, no. 2, pp. 551–558, 2015.

6. N. Beyraghi, A. Khoei, and K. Hadidi, “CMOS design of a four-quadrant multiplier based on a novel squarer circuit,” Analog Integr. Circuits Signal Process., vol. 80, no. 3, pp. 473–481, 2014.

7. M. A. Hashiesh, S. A. Mahmoud, and A. M. Soliman, “New four-quadrant CMOS current-mode and voltage-mode multipliers,” Analog Integr. Circuits Signal Process., vol. 45, no. 3, pp. 295–307, 2005.

8. A. Naderi, A. Khoei, K. Hadidi, and H. Ghasemzadeh, “A new high speed and low power four-quadrant CMOS analog multiplier in current mode,” AEU - Int. J. Electron. Commun., vol. 63, no. 9, pp. 769–775, Sep. 2009.

9. S. Mowlavi, A. Baharmast, J. Sobhi, and Z. D. Koozehkanani, “A novel current-mode low-power adjustable wide input range four-quadrant analog multiplier,” Integration, vol. 63, no. April, pp. 130–137, 2018.

10. T. Aghaei and A. Naderi Saatlo, “A new strategy to design low power translinear based CMOS analog multiplier,” Integration, no. March, Apr. 2019.

11. E. Ibaragi, A. Hyogo, and K. Sekine, “CMOS analog multiplier free from mobility reduction and body effect,” Analog Integr. Circuits Signal Process., vol. 25, no. 3, pp. 281–290, 2000.

12. A. Ü. Keskin, “A four quadrant analog multiplier employing single CDBA,” Analog Integr. Circuits Signal Process., vol. 40, no. 1, pp. 99– 101, 2004.

13. G. Colli and F. Montecchi, “Low voltage low power CMOS four-quadrant analog multiplier for neural network applications,” Proc. - IEEE Int. Symp. Circuits Syst., vol. 1, pp. 496–499, 1996.

14. A. Panigrahi and P. K. Paul, “A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion,” Analog Integr. Circuits Signal Process., vol. 75, no. 2, pp. 237–243, 2013.

15. S. Soltany and A. Rezai, “A novel low power and low voltage bulk-input four-quadrant analog multiplier in voltage mode,” Int. J. Multimed. Ubiquitous Eng., vol. 11, no. 1, pp. 159–168, 2016.

16. Y. Babacan, “Ultra-low voltage and low-power voltage-mode DTMOS-based four-quadrant analog multiplier,” Analog Integr. Circuits Signal Process., vol. 99, no. 1, pp. 39–45, 2019.

17. V. Niranjan and M. Gupta, “Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors,” Microelectron. Int., vol. 26, no. 1, pp. 47–52, Jan. 2009.

18. A. Chaudhry, V. Niranjan, and A. Kumar, “Bandwidth extension of analog multiplier using dynamic threshold MOS transistor,” Proc. - 2014 3rd Int. Conf. Reliab. Infocom Technol. Optim. Trends Futur. Dir. ICRITO 2014, pp. 1–4, 2015.

19. S. Keleş and H. H. Kuntman, “Four quadrant FGMOS analog multiplier,” Turkish J. Electr. Eng. Comput. Sci., vol. 19, no. 2, pp. 291–301, 2011.

20. S. Keleş and F. Keleş, “Ultra low power wide range four quadrant analog multiplier,” Analog Integr. Circuits Signal Process., vol. 1, 2019.

21. M. M. Maryan, S. J. Azhari, and A. Ghanaatian, “Low power FGMOS-based four-quadrant current multiplier circuits,” Analog Integr. Circuits Signal Process., vol. 95, no. 1, pp. 115–125, 2018.

22. S. Vlassis and S. Siskos, “Design of Voltage-Mode and Current-Mode Computational Circuits Using Floating-Gate MOS Transistors,” vol. 51, no. 2, pp. 329–341, 2004.

23. M. Ismail and T. Fiez, Analog VLSI Signal and Information Processing. New York, USA: McGraw-Hill Education, 1994.

24. Yan Shouli and E. Sanchez-sinencio, “Low voltage analog circuit design techniques: A Tutorial,” IEICE TRANS. Analog Integr. CIRCUITS Syst., vol. E00-A, no. 2, pp. 1–17, 2000.

25. C. T. Sah, “Characteristics of the metal-Oxide-semiconductor transistors,” IEEE Trans. Electron Devices, vol. 11, no. 7, pp. 324–345, Jul. 1964.

26. B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, “Designing 1-V Op amps using standard digital CMOS technology,” IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., vol. 45, no. 7, pp. 769–780, 1998.

27. M. Rakús, V. Stopjaková, and D. Arbet, “Design techniques for low-voltage analog integrated circuits,” J. Electr. Eng., vol. 68, no. 4, pp. 245–255, Aug. 2017.

28. S. S. Rajput and S. S. Jamuar, “Low Voltage Design Techniques,” IEEE Circuits Syst. Mag., vol. 2, no. 1, pp. 24–42, 2002.

29. G. Zamora-Mejia, A. Diaz-Armendariz, H. Santiago-Ramirez, J. M. Rocha-Perez, C. A. Gracios-Marin, and A. Diaz-Sanchez, “Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier,” Circuits, Syst. Signal Process., vol. 38, no. 4, pp. 1547–1560, 2019.

30. B. Boonchu and W. Surakampontorn, “CMOS voltage-mode analog multiplier,” in 2006 IEEE International Symposium on Circuits and Systems, 2006, vol. 1, no. 5, p. 4.

31. B. Boonchu and W. Surakampontorn, “CMOS class-AB voltage-mode multiplier,” Isc. 2005 - Int. Symp. Commun. Inf. Technol. 2005, Proc., vol. I, no. 3, pp. 1489–1492, 2005.

32. F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P. K. Ko, and C. Hu, “A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation,” IEEE Electron Device Lett., vol. 15, no. 12, pp. 510–512, 1994.

33. F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P. K. Ko, and Chenming Hu, “A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation,” IEEE Electron Device Lett., vol. 15, no. 12, pp. 510–512, Dec. 1994.

34. F. Assaderaghi, D. Sinitsky, S. a. Parke, J. Bokor, and P. K. Ko, “Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 414–422, Mar. 1997.

35. C. Wann, F. Assaderaghi, R. Dennard, G. Shahidi, and Y. Taur, “Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET,” Int. Electron Devices Meet. Tech. Dig., pp. 113–116, 1996.

36. F. Assaderaghi, “DTMOS: its derivatives and variations, and their potential applications,” ICM 2000. Proc. 12th Int. Conf. Microelectron. (IEEE Cat. No.00EX453), pp. 9–10, 2000.

37. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and Chenming Hu, “A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation,” in Proceedings of 1994 IEEE International Electron Devices Meeting, 1994, pp. 809–812.

38. M. E. Başak and F. Kaçar, “Ultra-low voltage VDBA design by using PMOS DTMOS transistors,” Istanbul Univ. - J. Electr. Electron. Eng., vol. 17, no. 2, pp. 3463–3469, 2017.