Ultra low-power DC voltage limiter for RFID application in 0.18-m CMOS technology

In this paper, a low-power DC voltage limiter is designed for radio frequency identi cation tags. In this design, the low-power bandgap reference (BGR) circuit, which is insensitive to temperature, and also the comparator are used for the voltage limiter circuit. To make the I-V curve approach the ideal one, four inverter stages are employed to the output of the comparator. The structure of the BGR and comparator use only MOSFET transistors that work in subthreshold region when the limiter is inactive. These two blocks have power consumption of 220 pW and 1300 pW, respectively. The limited output voltage is 1.5 V and the current consumption when the tag and the reader are far from each other is 31.56 nA, which is very insigni cant compared with the total current consumption of the tag. The chip area of the voltage limiter circuit is 1936 m 2 . The simulation is done in 0.18- m CMOS technology and the operational frequency is 960 MHz.

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