İsa Ahmet GÜNEY, Merve YILDIZ GÜNEY, Gürhan KÜÇÜK, Nazlı TOKATLI, Uğur NEZİR

ShapeShifter: a morphable microprocessor for low power

A composite core contains large and small heterogeneous microengines. The most important property of composite cores is their ability to select the most proper microengine for running applications to save power without sacrificing too much performance. To achieve this, a composite core tries to predict the performance of the passive microengine by collecting various processor statistics from the active microengine at runtime. In the method proposed in the literature, the microengine, which is more ideal for running the rest of the application, is determined by a migrationdecision circuitry that is bound to collected statistics and complex functions, which are run in a sequential manner. In this study, we propose the ShapeShifter architecture that holds a single out-of-order core to switch its mode of instruction execution between out-of-order and in-order modes. With a simple mode-change decision circuitry, which is bound to only two processor statistics, we can save more than 25% power, more than 21% on energy-delay product, and more than 16% on energy-delay-square product on the average, by only sacrificing less than 5% of performance.

PDF

___

[1] Lukefahr A, Padmanabha S, Das R, Sleiman FM, Dreslinski RG et al. Composite cores: Pushing heterogeneity into a core. In: 45th Annual IEEE/ACM International Symposium on Microarchitecture; Vancouver, BC, Canada; 2012. pp. 317-328.
[2] Lukefahr A, Padmanabha S, Das R, Sleiman FM, Dreslinski RG et al. Exploring fine-grained heterogeneity with composite cores. IEEE Transactions on Computers 2015; 65 (2): 535-547.
[3] Binkert N, Beckmann B, Black G, Reinhardt SK, Saidi A et al. The gem5 simulator. SIGARCH Computer Architecture News 2011; (39):1-7.
[4] Henning, JL. SPEC CPU2006 benchmark descriptions. SIGARCH Computer Architecture News 2006; (34):1-17.
[5] Ghiasi S, Casmira J, Grunwald D. Using IPC variation in workloads with externally specified rates to reduce power consumption. In: Workshop on Complexity Effective Design, Vancouver, BC, Canada, 2000.
[6] Albonesi DH, Balasubramonian R, Dropsbo SG, Dwarkadas S, Friedman EG et al. Dynamically tuning processor resources with adaptive processing. Computer 2013;36 (12): 49-58.
[7] Manne S, Klauser A, Grunwald D. Pipeline gating: speculation control for energy reduction In: Proceedings of the 25th Annual International Symposium on Computer Architecture; Barcelona, Spain; 1998. pp. 132-141.
[8] Morancho E, Llaberia JM, Olive A. On reducing energy-consumption by late-inserting instructions into the issue queue. In: Proceedings of the 2007 International Symposium on Low power Electronics and Design; Portland, OR, USA; 2007. pp. 371-374.
[9] Homayoun H, Kontorinis V, Shayan A, Lin T, Tullsen DM. Dynamically heterogeneous cores through 3D resource pooling. In: IEEE International Symposium on High-Performance Computer Architecture; New Orleans, LA, USA; 2012. pp. 1-12.
[10] Afram F, Ghose K. FlexCore: A reconfigurable processor supporting flexible, dynamic morphing. In: Proceedings of the IEEE 22nd International Conference on High Performance Computing (HiPC); Bengaluru, India; 2015. pp. 30-39.
[11] Sembrant A, Carlson T, Hagersten E, Black-Shaffer D, Perais A et al. Long term parking (LTP): criticality-aware resource allocation in OOO processors. In: Proceedings of the 48th International Symposium on Microarchitecture; Waikiki Hawaii; 2015.pp. 334-346.
[12] Sleiman FM, Wenisch TF. Efficiently scaling out-of-order cores for simultaneous multithreading. SIGARCH Computer Architecture 2016;44:431-443.
[13] Lebeck AR, Koppanalil J, Li T, Patwardhan J, Rotenberg E. A large, fast instruction window for tolerating cache misses. In: Proceedings 29th Annual International Symposium on Computer Architecture; Anchorage, Alaska, USA; 2002. pp. 59-70.
[14] Hubner M, Tradowsky C, Gohringer D, Braun L, Thoma F et al. Dynamic processor reconfiguration. In: International Conference on Reconfigurable Computing and FPGAs; Cancun, Mexico; 2011. pp.123-128.
[15] Carlson TE, Heirman W, Allam O, Kaxiras S, Eeckhout L. The load slice core microarchitecture. In: ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA); Portland, Oregon; 2015. pp. 272-284.
[16] Suleman MA, Hashemi M, Wilkerson C, Patt YN. Morphcore: An energy-efficient microarchitecture for high performance ilp and high throughput tlp. In: 45th Annual IEEE/ACM International Symposium on Microarchitecture; Vancouver, BC, Canada; 2012. pp. 305-316.
[17] Kumar R, Tullsen DM, Ranganathan P, Jouppi NP, Farkas KI. Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. In: Proceedings 31st Annual International Symposium on Computer Architecture; Munich, Germany; 2004. pp. 64-75.
[18] Bahar RI, Manne S. Power and energy reduction via pipeline balancing. In: Proceedings of the 28th Annual International Symposium on Computer Architecture; Göteborg, Sweden; 2001. pp. 218-229.
[19] Kumar R, Jouppi NP, Tullsen DM. Conjoined-core chip multiprocessing. In: Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture; Cambridge, UK; 2014. pp. 195-206.
[20] Kim C, Sethumadhavan S, Govindan MS, Ranganathan N, Gulati D et al. Composable lightweight processors. In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO); Chicago, IL, USA; 2007. pp. 381-394.
[21] Ipek E, Kirman M, Kirman N, Martinez JF. Core fusion: accommodating software diversity in chip multiprocessors. SIGARCH Computer Architecture News 2007;35:186-197
[22] Savas ME, Guney IA, Tokatli NN, Kisinbay B, Kucuk G. iMODE (interactive mood detection engine) processor. In: 4th International Conference on Computer Science and Engineering (UBMK); Samsun, Turkey; 2019. pp. 1-6.