Janakiraman NITHIYANANTHAM, Nirmal Kumar PALANISAMY

An experimental study of coarse-grained reconfigurable system-on-chip-based software-defined radio

: Software-defined radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modifiable software or firmware. This paper describes the coarse-grained reconfigurable array (CGRA) implementations of SDR architecture. This architecture is an extension of traditional SDR in complex adaptation strategies, such as highly reliable communications and efficient utilization of the resources and spectrum upgrade, through its internal states (performance) and hardware architecture. The proposed CGRA-based SDR implementation is based on dynamic partial reconfiguration methodology, which has the capability of reusing the same hardware module to handle different algorithms. This CGRA-based SDR provides greater flexibility and adds new abilities without additional cost. Initially, the SDR system was simulated in the Agilent SystemVue environment to analyze the error boundaries of the proposed SDR architecture. Then the SDR system was coded in the Verilog hardware description language and implemented on top of CGRAs such as the MOLEN, MORPHOSYS, and ADRES reconfigurable system-on-chip (SoC) architectures. These SoC architectures were installed within the Xilinx Virtex 5 field-programmable gate array to analyze the performance of SDR architectures in terms of area utilization, operational speed, power optimization, reconfiguration time, coprocessor execution time, preemption support, and relocation support of the system. The performance analysis indicates that the ADRES SoC architecture is suitable for dynamic partial reconfiguration and the MOLEN SoC architecture is more suitable for power, area, and speed requirements and low circuit complexity compared to other architectures

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[1] Ackley DH, Williams LR. Homeostatic architectures for robust spatial computing. In: IEEE 2011 Conference on Self-Adaptive and Self-Organizing Systems Workshops; 37 October 2011; Ann Arbor, MI, USA. New York, NY, USA: IEEE. pp. 9196.
[2] Ebeling C, Cronquist DC, Franklin P. RaPiDReconfigurable pipelined datapath. In: Hartenstein RW, Glesner M, editors. International Workshop on Field-Programmable Logic and Applications. Berlin, Germany: Springer-Verlag, 1996. pp. 126135.
[3] Mirsky E, DeHon A. MATRIXA reconfigurable computing architecture with configurable instruction distribution and deployable resources. In: IEEE Symposium on FPGAs for Custom Computing Machines; 1719 April 1996; Napa Valley, CA, USA. New York, NY, USA: IEEE. pp. 157166.
[4] Minev PB, Kukenska VS. The Virtex-5 routing and logic architecture. In: Proceedings of the 18th International Scientific and Applied Science Conference of Electronics; 1417 September 2009; Sozopol, Bulgaria. pp. 107110.
[5] Lenart T. Design of reconfigurable hardware architectures for real-time applicationsmodeling and implementation. PhD, Lund University, Lund, Sweden, 2008.
[6] Mueck M, Piipponen A, Kallioj¨arvi K, Dimitrakopoulos G, Tsagkaris K, Demestichas P, Casadevall F, P´eerezRomero J, Sallent O, Baldini G et al. ETSI reconfigurable radio systems-status and future directions on software defined radio and cognitive radio standards. IEEE Commun Mag 2010; 48: 7886.
[7] Ulversøy T. Software defined radio: challenges and opportunities. IEEE Commun Surveys Tuts 2010; 12: 531550.
[8] Minden GJ, Evans JB, Searl L, DePardo D, Petty VR, Rajbanshi R, Newman T, Chen Q, Weidling F, Guffey J et al. KUAR: a flexible software-defined radio development platform. In: IEEE 2007 International Symposium on Dynamic Spectrum Access Networks; 1720 April 2007; Dublin, Ireland. New York, NY, USA: IEEE. pp. 428439.
[9] Raja J, Kannan M. VLSI implementation of high throughput MIMO-OFDM transceiver for 4th generation systems. Indian J Eng Mater Sci 2012; 19: 307319.
[10] Yoshizawa S, Miyanaga Y. VLSI Implementation of a 600-Mbps MIMO-OFDM wireless communication system. In: IEEE Asia Pacific Conference on Circuits and Systems; 47 December 2006; Singapore, Singapore. New York, NY, USA: IEEE. pp. 9396.
[11] Ogasawara Y, Odagiri S, Yoshizawa S, Miyanaga Y. Performance evaluation of environment-adaptive agent system in OFDM cognitive radio. In: International Symposium on Intelligent Signal Processing and Communication Systems; 811 February 2009; Bangkok, Thailand. New York, NY, USA: IEEE. pp. 14.
[12] Taha HJ, Salleh MFM. Multi-carrier transmission techniques for wireless communication systems: a survey. WSEAS T Commun 2009; 8: 457472.
[13] Singh H, Lee MH, Lu G, Kurdahi FJ, Bagherzadeh N, Chaves Filho EM. MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE T Comput 2000; 49: 465481.
[14] Vassiliadis S, Wong S, Gaydadjiev G, Bertels K, Kuzmanov G, Panainte EM. The MOLEN polymorphic processor. IEEE T Comput 2004; 53: 13631375.
[15] Wu K, Kanstein A, Madsen J, Berekovic M. MT-ADRES: multithreading on coarse-grained reconfigurable architecture. Int J Electron 2008; 95: 761776.
[16] Schiff M. Signal and algorithm development environment for SDR. In: IEEE Military Communications Conference; 2831 October 2001; Tysons Corner, VA, USA. New York, NY, USA: IEEE. pp. 225229.
[17] Zheng L, Tse DNC. Diversity and multiplexing: a fundamental tradeoff in multiple-antenna channels. IEEE T Inform Theory 2003; 49: 10731096.
[18] H¨aring L, Chen Y, Czylwik A. Automatic modulation classification methods for wireless OFDM systems in TDD mode. IEEE T Commun 2010; 58: 24802485.
[19] J´o´zwiak L, Nedjah N, Figueroa M. Modern development methods and tools for embedded reconfigurable systems: a survey. Integration 2010; 43: 133.
[20] Marwedel P. Embedded System Design: Embedded Systems Foundations of Cyber-Physical Systems. 2nd ed. Dordrecht, Germany: Springer, 2011.
[21] Janakiraman N, Nirmal Kumar P. Multi-objective module partitioning design for dynamic and partial reconfigurable system-on-chip using genetic algorithm. J Syst Architect 2014; 60: 119139.
[22] Lee J, Chung MK, Cho YG, Ryu S, Ahn JH, Choi K. Mapping and scheduling of tasks and communications on many-core SoC under local memory constraint. IEEE T Comput Aid D 2013; 32: 17481761.
[23] Koch D, Beckhoff C, Torrison J. Fine-grained partial runtime reconfiguration on Virtex-5 FPGAs. In: IEEE 2010 Annual International Symposium on Field-Programmable Custom Computing Machines; 24 May 2010; Charlotte,NC, USA. New York, NY, USA: IEEE. pp. 6972.
[24] Di Carlo S, Gambardella G, Indaco M, Prinetto P, Rolfo D, Trotta P. Dependable dynamic partial reconfiguration with minimal area and time overheads on Xilinx FPGAS. In: Proceedings of the 23rd International Conference on Field Programmable Logic and Applications; 24 September 2013; Porto, Portugal. New York, NY, USA: IEEE.pp. 14.
[25] Rauwerda GK. Multi-standard adaptive wireless communication receivers: adaptive applications mapped on heterogeneous dynamically reconfigurable hardware. PhD, University of Twente, Enschede, the Netherlands, 2008.
[26] Roberto A. Design and implementation of software defined radios on a homogeneous multi-processor architecture. DSc, Tampere University of Technology, Tampere, Finland, 2013.
[27] Wu C, Cen F, Cai H. A high-performance heterogeneous embedded signal processing system based on serial RapidIO interconnection. In: IEEE 2010 International Conference on Computer Science and Information Technology; 911 July 2010; Chengdu, China. New York, NY, USA: IEEE. pp. 611614.
[28] Krill B, Ahmad A, Amira A, Rabah H. An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores. Signal Process-Image 2010; 25: 377387.
[29] Venkatasubramanian V. Hardware support for dynamic partial reconfigurationaccelerating multiple functions. MSc, Delft University of Technology, Delft, the Netherlands, 2011.