Khouloud BOUAZIZ, Abdulfattah M. OBEID, Mohamed ABID, Sonda CHTOUROU

A review on embedded field programmable gate array architectures and configuration tools

Nowadays, systems-on-chip have reached a level where nonrecurring engineering costs have become a greatchallenge due to the increase of design complexity and postfabrication errors. Embedded field programmable gate arrays(eFPGAs) represent a viable alternative to overcome these issues since they provide postmanufacturing flexibility thatcan reduce the number of chip redesigns and amortize chip fabrication cost. In this paper, we present an overviewon eFPGAs and their architectures, computer aided design (CAD) tools, and design challenges. An eFPGA must bewell-designed and accompanied by an optimized CAD tool suite to respond to target application’s requirements in termsof power consumption, area, and performance. In this survey, we studied coarse-grained eFPGAs with customized blockswhich are used for domain-specific applications and fine-grained eFPGAs that are used for general purposes but havelower performance.

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[1] Kuon I, Rose J. Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 2007; 26 (2): 203-215. doi: 10.1109/TCAD.2006.884574
[2] Wilton SJE, Kafafi N, Wu JCH, Bozman KA, Aken’Ova VO et al. Design considerations for soft embedded programmable logic cores. IEEE Journal of Solid-State Circuits 2005; 40 (2): 485-497. doi: 10.1109/JSSC.2004.841038
[3] Li A, Wentzlaff D. PRGA: An open-source framework for building and using custom FPGAs. In: The First Workshop on Open-Source Design Automation; Florence, Italy; 2019. pp. 1-6.
[4] Chtourou S, Marrakchi Z, Amouri E, Pangracious V, Abid M et al. Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish Journal of Electrical Engineering and Computer Sciences 2017; 25 (3): 2044-2054. doi: 10.3906/elk-1506-51
[5] Gaillardon PE, Tang X, Kim G, De Micheli G. A novel FPGA architecture based on ultrafine grain reconfigurable logic cells. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015; 23 (10): 2187-2197. doi: 10.1109/TVLSI.2014.2359385
[6] Rose J, Luu J, Yu CW, Densmore O, Goeders J et al. The VTR project: architecture and CAD for FPGAs from verilog to routing. In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays; Monterey, CA, USA; 2012. pp. 77-86.
[7] Yuan FL, Wang CC, Yu TH, Marković D. A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing. IEEE Journal of Solid-State Circuits 2015; 50 (1): 137-149. doi: 10.1109/JSSC.2014.2372034
[8] Marrakchi Z, Mrabet H, Farooq U, Mehrez H. FPGA interconnect topologies exploration. International Journal of Reconfigurable Computing 2009; 2009 (6): 1-13. doi: 10.1155/2009/259837
[9] Hutton M, Adibsamii K, Leaver A. Timing-driven placement for hierarchical programmable logic devices. In: Proceedings of the 2001 ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays; Monterey, CA, USA; 2001. pp. 3-11.
[10] Lai YT, Wang PT. Hierarchical interconnection structures for field programmable gate arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1997; 5 (2); 186-196. doi: 10.1109/92.585219
[11] Syed Zahid A. eFPGAs: Architectural explorations, system integration and a visionary industrial survey of programmable technologies. PhD, University of Montpellier, Montpellier, France, 2011.
[12] Hutton M. The design of modern FPGA Architectures. In: International Symposium The Future of Configurable Hardware; Gent, Belgium; 2004.pp.1-10.
[13] Singh H, Lee MH, Lu G, Kurdahi FJ, Bagherzadeh N et al. MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers 2000; 49 (5): 465-481. doi: 10.1109/12.859540
[14] Becker J, Glesner M. A parallel dynamically reconfigurable architecture designed for flexible application-tailored hardware/software systems in future mobile communication. The Journal of Supercomputing 2001; 19 (1): 105-127. doi: 10.1023/A:1017456815823
[15] Zhang H, Prabhu V, George V, Wan M, Benes M et al. A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications. In: IEEE International Solid-State Circuits Conference; San Francisco, CA, USA; 2000. pp. 68-69.
[16] Obeid AM, Qasim SM, BenSaleh MS, AlJuffri A. HyDRA: hybrid dynamically reconfigurable architecture for DSP applications. IEICE Transactions on Electronics 2016; 99 (7): 866-877. doi: 10.1587/transele.E99.C.866
[17] Phillips S, Hauck S. Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays; Monterey, CA, USA; 2002. pp. 165-173.
[18] Borgatti M, Lertora F, Forêt B, Calí L. A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O. IEEE Journal of Solid-State Circuits 2003; 38 (3): 521-529. doi: 10.1109/JSSC.2002.808288
[19] Schewel J. A hardware/software co-design system using configurable computing technology. In: Parallel Processing Symposium; Orlando, FL, USA; 1998. pp. 620-625.
[20] Aken’Ova VO. Bridging the gap between soft and hard eFPGA design. PhD, University of British Columbia, Canada, 2005.
[21] Aken’Ova VC, Lemieux G, Saleh R. An improved ”soft” eFPGA design and implementation strategy. In: International Conference on Application-specific Systems, Architectures and Processors; San Jose, CA, USA; 2006. pp. 125-131.
[22] von Sydow T, Neumann B, Blume H, Noll TG. Quantitative analysis of embedded FPGA-architectures for arithmetic. In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference; Steamboat Springs, CO, USA; 2005. pp. 179-182.
[23] Lodi A, Cappelli A, Bocchi M, Mucci C, Innocenti M et al. XiSystem: a XiRisc-based SoC with reconfigurable IO module. IEEE Journal of Solid-State Circuits 2006; 41 (1): 85-96. doi: 10.1109/JSSC.2005.859319
[24] Lodi A, Toma M, Campi F. A pipelined configurable gate array for embedded processors. In: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays; Monterey, California, USA; 2003. pp. 21-30.
[25] Mucci C, Chiesa C, Lodi A, Toma M, Campi F. A C-based algorithm development flow for a reconfigurable processor architecture. In: International Symposium on System-on-Chip; Tampere, Finland; 2003. pp. 69-73.
[26] Syed Zahid A, Julien E, Laurent R, Jean-Baptiste C, Gilles S et al. Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. In: Proceedings of the Conference on Design, Automation and Test in Europe; Nice, France; 2009. pp. 184-189.
[27] Yuan FL, Wang CC, Yu TH, Marković D. A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing. IEEE Journal of Solid-State Circuits 2015; 50 (1): 137-149. doi: 10.1109/JSSC.2014.2372034
[28] Nassimi D, Sahni S. A self-routing Benes network and parallel permutation algorithms. IEEE Transactions on computers 1981; C-30 (5): 332-340. doi: 10.1109/TC.1981.1675791
[29] Balkan AO, Qu G, Vishkin U. Mesh-of-trees and alternative interconnection networks for single-chip parallelism. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2009; 17 (10): 1419-1432. doi: 10.1109/TVLSI.2008.2003999