A process-tolerant low-power adder architecture for image processing applications

The aggressive CMOS technology scaling in the sub-100-nm regime leads to highly challenging VLSI designdue to the presence of unreliable components. The delay failures in arithmetic units are increasing rapidly due to theincreased effect of process variation (PV) in scaled technology. This paper introduces a novel process-tolerant lowpower adder (Prot-LA) architecture for error-tolerant applications. The proposed Prot-LA architecture segments theoperands into two parts and computes addition of the upper parts in carry-propagate, whereas it computes the lowerparts in a carry-free manner. In the Prot-LA, the number of bits in carry-propagate and carry-free additions can bereconfigured based on the amount of PV. An on-chip PV detector is embedded to determine the PV severity. Becauseof this reconfigurability, the proposed adder completes the carry propagation with minimum error even under severeprocess variation. The simulation results show that proposed Prot-LA provides 19.9% reduced power consumption overthe state-of-the-art approximate adder. The efficacy of the proposed adder is demonstrated in the real application bydesigning an image scaling processor (ISP). The simulation results show that the Prot-LA embedded ISP consumes 7.75%reduced energy with 2.43 dB higher PSNR over the existing approximate adder embedded ISP.

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