Salah ALKURWY, Sawal ALI, Shabiul ISLAM, Faizul IDROS

A low power memoryless ROM design architecture for a direct digital frequency synthesizer

This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: /2) of the sine wave. The ROM is partitioned into three four-bit sub-ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24- bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub-ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.

PDF

___

[1] Tierney C, Rader M, Gold B. A digital frequency synthesizer. IEEE T Acoust Speech 1971; 19: 48-57.
[2] Jung H, Yoo T, Cho J, Baek H. Pipelined phase accumulator using sequential FCW loading scheme for DDFS. Electr Lett 2012; 48: 1044-1046.
[3] Kim S, Lee J, Hong Y, Kim E, Baek H. Low-power pipelined phase accumulator with sequential clock gating for DDFSs. Electr Lett 2013; 49: 1445-1446.
[4] B. Jensen S, Khafaji M, Johansen K, Krozer V, Scheytt C. Twelve-bit 20-GHz reduced size pipeline accumulator in 0.25 m SiGe:C technology for direct digital synthesiser applications. IET Circ Device Syst 2012; 6: 19-27.
[5] Ching Y, Jun W, Hsuan C. A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer. Chinese Sci Bull 2012; 57: 2480-2487.
[6] Sunderland A, Strauch A, Whar eld S, Peterson T, Cole R. CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications. IEEE J Solid-St Circ 1984; 19: 497-506.
[7] Hutchinson J. Contemporary Frequency Synthesis Techniques. New York, NY, USA: IEEE Press, 1975.
[8] Brown S, Vranesic Z. Fundamentals of Digital Logic with VHDL. 2nd ed. New York, NY, USA: McGraw-Hill, 2005.
[9] Alkurwy S, Sawal A, Islam S. Implementation of low power compressed ROM for direct digital frequency synthe- sizer. In: IEEE 2014 International Conference on Semiconductor Electronics; 27{29 August 2014; Kuala Lumpur, Malaysia. New York, NY, USA: IEEE. pp. 309-312.
[10] Curticapean F, Niittylahti J. A hardware efficient direct digital frequency synthesizer. In: IEEE 2001 International Conference on Electronics Circuits and Systems; 2{5 September 2001; Valetta, Malta. New York, NY, USA: IEEE. pp. 51-54.
[11] Yang BD, Choi JH, Han SH, Kim LS, Yu HK. An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/A converter. IEEE J Solid-St Circ 2004; 39: 761-774.
[12] De Caro D, Strollo M. High-performance direct digital frequency synthesizers using piecewise-polynomial approxi- mation. IEEE T Circ Syst-I 2005; 52: 324-337.
[13] De Caro D, Petra N, Strollo M. Reducing lookup-table size in direct digital frequency synthesizers using optimized multipartite table method. IEEE T Circ Syst-I 2008; 55: 2116-2127.
[14] NourEldin M, Yahia M. A novel low-power high-resolution ROM-less DDFS architecture. Int J Adv Res Electron 2013; 2: 990-994.
[15] Hsu H, Wang C. ROM-less DDFS using non-equal division parabolic polynomial interpolation method. In: IEEE 2011 International Symposium on Integrated Circuits; 12{14 December 2011; Singapore, Singapore. New York, NY, USA: IEEE. pp. 59-62.
[16] Ibrahim S, Sawal A, Islam S. Hardware implementation of 32-bit high-speed direct digital frequency synthesizer. Sci World J 2014; 131568.
[17] Alonso A, Miyahara M, Matsuzawa A. A novel direct digital frequency synthesizer employing complementary dual- phase latch-based architecture. In: IEEE 2015 International Conference on ASIC; 3{6 November 2015; Chengdu, China. New York, NY, USA: IEEE. pp. 1-4.
[18] Guo X, Wu D, Zhou L, Liu H, Wu J, Liu X. A 4-GHz 32-bit direct digital frequency synthesizer in 0.25 m SiGe HBT with SFDR > 46 dBc up to Nyquist bandwidth. In: IEEE 2016 Bipolar/BiCMOS Circuits and Technology Meeting; 25{27 September 2016; New Brunswick, NJ, USA. New York, NY, USA: IEEE. pp. 86-89.