Burak Berk ÜSTÜNDAĞ, Husam ALZAQ

A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform(DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two keymultiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS).Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection ofthe proper algorithm and implementation of multilevel DAA- and RNS-based DWT. The design has been implementedand synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6’s embedded block RAMs. The results revealthat the DAA-based approach is appropriate for a small number of filter taps, while the RNS-based approach would bemore appropriate for more than 10 filter taps, yet both DAA- and RNS-based approaches offer high signal quality withpeak signal-to-noise ratio as 73.5 and 56.5 dB, respectively

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