Embedded systems have geared up their applications in the field of smart phones, mobile devices, automobiles, and medical instrumentation. Along with the growth of technology, the functional requirements of the systems have also grown multifold. To accommodate these ever increasing functional requirements, the hardware should be designed to include the maximum capability, which in turn increases power consumption. Thus this has to be dynamically managed using software techniques. The dynamic voltage and frequency scaling (DVFS) feature provided in most of the recent processors has enabled power optimization through software. With this feature the processor operating frequency can be reduced on the fly through software. This paper proposes two approaches. In the first one, the hyper period-based method (HPBM), the slow down factor is calculated for the hyper period and the second method involves applying uniform slow down with frequency inheritance (USFI) with a hyper plane exact test (HET). Both approaches aim to calculate slow down factors for the tasks to be executed in the processors with the DVFS feature. The main objective of this work is to provide energy optimized scheduling as well as to minimize the overheads in slow down factor calculations.