Tajinder Pal SİNGH

14999

Speed optimization of 32 bit single precision floating point multiplier through pipelining in VHDL

Speed optimization of 32 bit single precision floating point multiplier through pipelining in VHDL

The paper is presenting the architectural method for speed optimization of floating point multiplier involves increasing the frequency by implementing pipelines in the design using VHDL language. The whole algorithm of IEEE 754 standard 32 bit single precision precision floating point multiplier have two pipelining stages, which improve the frequency rate of clock to 422.556 MHz and result the output in 2.367ns. The design also handles the overflow/ underflow cases with normalization for the better accuracy of the result. Xilinx vertex 5 FPGA is targeted for the design and the simulation is done on Xilinx ISE simulator.
Keywords:

Floating Point multiplier, VHDL, Pipelining Xilinx ISE tool,

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  • [1] IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008.[2] Mohamed Al-Ashrafy, Ashraf Salem and Wagdy Anis, “An efficient implementation of floating point multiplier” 2011 IEEE.[3] B.Sreenivasa Ganesh, J.E.N. Abhilash and G.Rajesh Kumar, “ Design and implemntation of floating point multiplier for better response” IJARCET,vol 1, issue 17, sep 2012.[4] Naresh Grover, M.K Soni., “ Design of FPGA based 32 bit floating point airthmetic unit and verfication of its VHDL code using MATLAB” I.J information engineering and electronics business ,feb 2014,MECS press[5] Ameya deshmukh and Pooja hatwalne, “ Design and implemenatatio time efficient floating point multiplier using VHDL, international journal of latestest trend in engineering and technology, vol 8 , issue 03, pp 084-090.
International Journal of Engineering Science and Application-Cover
  • ISSN: 2548-1185
  • Başlangıç: 2016
  • Yayıncı: Nişantaşı Üniversitesi
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