Design and Implementation of Area and Power Efficient Reconfigurable FIR Filter with Low Complexity Coefficients

This paper presents the design and implementation of area and power efficient reconfigurablefinite impulse response (FIR) filter. We present a method for designing a reconfigurable filterwith low binary complexity coefficients (LBCC) and thus to optimize the filter while satisfyingthe design specifications. The total number of non zero binary bits is taken as a measure of thebinary complexity (BC) of a coefficient. We propose two implementation architectures namelysigned-magnitude architecture (SMA) and signed-decimal architecture (SDA) which are basedon 3-bit binary common sub expression elimination (BCSE) algorithm and vertical horizontalBCSE (VHBCSE) algorithm respectively. SMA and SDA reduce the redundant computations ofthe coefficient multiplications in the filter. The proposed filters are synthesized on tsmc 65nmCMOS technology. The synthesis results show that the proposed filters are area and powerefficient when compared with the existing ones.

PDF

___

Hentschel, T., Fettweis, G., “Software radio receivers”, CDMA techniques for third generation mobile systems, Springer, 257-283, (1999).
Hentschel, T., Henker, M., Fettweis, G., “The digital front-end of software radio terminals”, IEEE Personal communications, 6(4): 40-46, (1999).
Dillinger, M., Madani, K., Alonistioti, N., Software defined radio: Architectures, systems and functions, John Wiley & Sons, (2005).
Singhal, S.K., Mohanty, B.K., “Efficient Parallel Architecture for Fixed-Coefficient and VariableCoefficient FIR Filters Using Distributed Arithmetic”, Journal of Circuits, Systems and Computers, 25(07): 1650073, (2016).
Hu, J., Huang, Z., Liu, C., Su, S., Zhou, J., “Design of Digital Channelizer Based on Source Number Estimation”, Journal of Circuits, Systems and Computers, 25(02): 1650008, (2016).
Hewlitt, R.M., Swartzlantler, E.S., “Canonical signed digit representation for FIR digital filters”, 2000 IEEE Workshop on Signal Processing Systems, SIPS 2000, Design and Implementation (Cat. No. 00TH8528), IEEE, 416-426, (2000).
Hashemian, R., “A new method for conversion of a 2's complement to canonic signed digit number system and its representation”, Conference Record of the Thirtieth Asilomar Conference on Signals, Systems and Computers, IEEE, 904-907, (1996).
He, S., Torkelson, M., “FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers”, Proceedings of the IEEE Custom Integrated Circuits Conference-CICC’94, IEEE, 81-84, (1994).
Chen, K.H., Chiueh, T.D., “A low-power digit-based reconfigurable FIR filter”, IEEE Transactions on Circuits and Systems II: Express Briefs, 53(8): 617-621, (2006).
Tang, Z., Zhang, J., Min, H., “A high-speed, programmable, CSD coefficient FIR filter”, IEEE Transactions on Consumer Electronics, 48(4): 834-837, (2002).
Muhammad, K., Roy, K., “Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(3): 292-300, (2002).
Park, J., Jeong, W., Mahmoodi-Meimand, H., Wang, Y., Choo, H., Roy, K., “Computation sharing programmable FIR filter for low-power and high-performance applications”, IEEE Journal of solidstate Circuits, 39(2): 348-357, (2004).
Voronenko, Y., Püschel, M., “Multiplierless multiple constant multiplication”, ACM Transactions on Algorithms (TALG), 3(2): 11, (2007).
Gustafsson, O., Dempster, A.G., “On the use of multiple constant multiplication in polyphase FIR filters and filter banks”, Proceedings of the 6th Nordic Signal Processing Symposium-NORSIG 2004, 53-56, (2004).
Mahesh, R., Vinod, A.P., “New reconfigurable architectures for implementing FIR filters with low complexity”, IEEE transactions on computer-aided design of integrated circuits and systems, 29(2): 275-288, (2010).
Hatai, I., Chakrabarti, I., Banerjee, S., “An Efficient VLSI Architecture of a Reconfigurable PulseShaping FIR Interpolation”, IEEE Transactions on very large scale integration (VLSI) systems, 23(6): 1150-1154, (2015).
Hatai, I., Chakrabarti, I., Banerjee, S., “An efficient constant multiplier architecture based on verticalhorizontal binary common sub-expression elimination algorithm for reconfigurable FIR filter synthesis”, IEEE Transactions on Circuits and Systems I: Regular Papers, 62(4): 1071-1080, (2015).
Skaf, J., Boyd, S.P., “Filter design with low complexity coefficients”, IEEE Transactions on Signal processing, 56(7): 3162-3169, (2008).
Boyd, S., Vandenberghe, L., Convex optimization, Cambridge university press, (2004).