A SINGLE/DOUBLE PRECISION FLOATING-POINT MULTIPLIER DESIGN FOR MULTIMEDIA APPLICATIONS

Keywords:

Multimedia floating-point numbers, multiply,

V. Lappalainen, T.D. Hämäläinen, P. Liuha, “Overview of Research Efforts on Media ISA Extensions and Their Usage in Video Coding”, IEEE Transactions on Circuits And Systems For Video Technology, Vol: 12, No: 8, 2002.
G. Even, S.M. Mueller, P.M. Seidel, “A dual mode IEEE multiplier Proceedings”, Second Annual IEEE International Conference, pp. 282- 289, 1997.
R.B. Lee, “Multimedia extensions for general purpose processors, Signal Processing Systems, 1997”, SIPS 97 - Design and Implementation., IEEE Workshop, pp. 9-23, 1997.
ANSI-IEEE Standard 754-1985: “IEEE Standard for binary floating-point arithmetic”, 1985.
Intel, “IA-32 Intel™ Architecture Software Developer’s Manual”, http://download.intel.com/ design/Pentium4/manuals/25366520.pdf, 2006. [6] Advanced
Architecture Programmers Manual”, White Paper, http://www.amd.com/usen/assets/content
type/white_papers_and_tech_docs/26569.pdf, 2006. Devices,
“AMD64 [7] K. Diefendorff, P.K. Dubey, R. Hochsprung, H. Scale, “AltiVec extension to PowerPC accelerates media processing”, IEEE Micro, Vol: 20 Iss: 2, pp. 85-95, 2000.
M.D. Jennings, T.M. Conte, “Subword Extensions for Video Processing on Mobile Systems”, IEEE Concurrency, Vol: 6, No: 3, pp. 13-16, 1998.
M. Gök, S. Krithivasan, M.J. Schulte, “Designs for Subword-Parallel Multiplications and Dot Product Operations”, Workshop on Application Specific Processors, pp. 27-31, 2004.