Abstract. A practical method enabling rapid development of an accurate device model for the PIW MOS capacitor is introduced. The simultaneous improvement in accuracy and development time can be achieved without having to perform extensive measurements on specialized test structures by taking advantage of the MOS transistor model parameters routinely extracted in support of analog circuit design activities. This method affords accurate modeling of the voltage coefficient of capacitance over the entire range of operating voltages. Furthermore, a compact subcircuit representation is proposed, which takes the distributed parasitic series resistance associated with the PIW capacitor into account, thereby allowing modeling of the limitations imposed on high-frequency performance as well as the quality factor. The validity of the proposed method is verified based on capacitance versus voltage measurements performed using a test vehicle fabricated in a submicron CMOS technology.