A Majority Gate Based RAM Cell Design With Least Feature Size In QCA

Designing and fabricating complementary metal-oxide semiconductor (CMOS) based logic devices at nanoscale faces serious issues like oxide thickness, thermal reliability, and energy dissipation. Hence the industries are in search of new technologies which could substitute the scaling down of CMOS circuits. Quantum-dot-cellular-automata (QCA) is an imminent technology considered at nano-level with the high speed of operation and lower power dissipation features. As the memory is used in most of the electronic equipment for data storage purpose, designing a RAM cell with a reduced number of QCA cells, and lower energy dissipation finds wide applications in the electronics industry. This paper first proposes a five input majority gate which may be utilized efficiently for designing single layer QCA circuits. Then by using the invented gate, a coplanar RAM cell structure with Set and Reset capability is devised. The structural and energy dissipation analysis of presented structures are estimated using QCADesigner and QCAPro tools. The results prove that the disclosed RAM cell architecture achieves 12.5% lower area, 18.26% lower total energy dissipation, and 16.6% lower input to output delay than the best-reported design.

PDF

___

[1] Compano, R., Molenkamp, L., & Paul, D. J., “Roadmap for Nano Electronics”, European Commission IST Programme, Future and Emerging Technologies, (2000).
[2] Bourianoff, G., “The future of nano computing”, Computer, 36(8): 44-53, (2003).
[3] Lent, C. S., & Tougaw, P. D., “A device architecture for computing with quantum dots”, Proceedings of the IEEE, 85(4): 541-57, (1997).
[4] Tougaw, P. D., & Lent, C. S., “Logical devices implemented using quantum cellular automata”, Journal of Applied Physics, 75(3): 1818-25, (1994).
[5] Huang, J., Momenzadeh, M., & Lombardi, F., “Design of sequential circuits by quantum-dot cellular automata”, Microelectronics Journal, 38(4-5): 525-37, (2007).
[6] Bahar, A. N., Rahman, M. M., Nahid, N. M., & Hassan, M. K., “Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata”, Data in Brief, 10: 557-60, (2017).
[7] Abdullah-Al-Shafi, M., & Bahar, A. N., “Ultra-efficient design of robust RS flip-flop in nanoscale with energy dissipation study”, Cogent Engineering, 4(1): 1391060, (2017).
[8] Sen, B., Goswami, M., Some, S., & Sikdar, B. K., “Design of sequential circuits in multilayer qca structure”, In 2013 International Symposium on Electronic System Design IEEE, 21-25, (2013).
[9] Abdullah-Al-Shafi, M., Bahar, A. N., Habib, M. A., Bhuiyan, M. M. R., Ahmad, F., Ahmad, P. Z., & Ahmed, K., “Designing single layer counter in quantum-dot cellular automata with energy dissipation analysis”, Ain Shams Engineering Journal, (2017).
[10] Walus, K., Dysart, T. J., Jullien, G. A., & Budiman, R. A., “QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata”, IEEE transactions on nanotechnology, 3(1): 26-31, (2004).
[11] https://www.mina.ubc.ca/qcadesigner, Visited on January (2017).
[12] Kim, K., Wu, K., & Karri, R., “Quantum-dot cellular automata design guideline”, IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, 89(6): 1607-14, (2006).
[13] Navi, K., Roohi, A., & Sayedsalehi, S., “Designing reconfigurable quantum-dot cellular automata logic circuits”, Journal of Computational and Theoretical Nano Science, 10(5): 1137-46, (2013).
[14] Campos, C. A. T., Marciano, A. L., Neto, O. P. V., & Torres, F. S., “USE: A universal, scalable, and efficient clocking scheme for QCA”, IEEE Transactions on computer-aided design of integrated circuits and systems, 35(3): 513-17, (2015).
[15] Vankamamidi, V., Ottavi, M., & Lombardi, F., “Two-dimensional schemes for clocking/timing of QCA circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(1): 34-44, (2007).
[16] Han, J., Boykin, E. R., Chen, H., Liang, J., & Fortes, J. A., “On the reliability of computational structures using majority logic”, IEEE Transactions on Nanotechnology, 10(5): 1099-1112, (2011).
[17] Navi, K., Sayedsalehi, S., Farazkish, R., & Azghadi, M. R., “Five-input majority gate, a new device for quantum-dot cellular automata”, Journal of Computational and Theoretical Nanoscience, 7(8): 1546-53, (2010).
[18] Navi, K., Farazkish, R., Sayedsalehi, S., & Azghadi, M. R., “A new quantum-dot cellular automata full-adder”, Microelectronics Journal, 41(12): 820-26, (2010).
[19] Hashemi, S., & Navi, K., “A novel robust QCA full-adder”, Procedia Materials Science, 11: 37680, (2015).
[20] Angizi, S., Sarmadi, S., Sayedsalehi, S., & Navi, K., “Design and evaluation of new majority gatebased RAM cell in quantum-dot cellular automata”, Microelectronics Journal, 46(1): 43-51, (2015).
[21] Farazkish, R., & Navi, K., “New efficient five-input majority gate for quantum-dot cellular automata”, Journal of Nanoparticle Research, 14(11): 1252, (2012).
[22] Farazkish, R., “A new quantum-dot cellular automata fault-tolerant five-input majority gate”, Journal of nanoparticle research, 16(2): 2259, (2014).
[23] Roohi, A., Khademolhosseini, H., Sayedsalehi, S., & Navi, K., “A symmetric quantum-dot cellular automata design for 5-input majority gate”, Journal of Computational Electronics, 13(3): 701-08, (2014).
[24] Sheikhfaal, S., Angizi, S., Sarmadi, S., Moaiyeri, M. H., & Sayedsalehi, S., “Designing efficient QCA logical circuits with power dissipation analysis”. Microelectronics Journal, 46(6): 462-71, (2015).
[25] Khosroshahy, M. B., Moaiyeri, M. H., Navi, K., & Bagherzadeh, N., “An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata”, Results in Physics, 7: 3543-51, (2017).
[26] Bahar, A. N., & Waheed, S., “Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata”, Springer Plus, 5(1): 636, (2016).
[27] Hashemi, S., & Navi, K., “New robust QCA D flip flop and memory structures”, Microelectronics Journal, 43(12): 929-40, (2012).
[28] Walus, K., Vetteth, A., Jullien, G. A., & Dimitrov, V. S., “RAM design using quantum-dot cellular automata”, In Nano Technology Conference (2): 160-63, (2003).
[29] Srivastava, S., Sarkar, S., & Bhanja, S., “Estimation of upper bound of power dissipation in QCA circuits”, IEEE transactions on nanotechnology, 8(1): 116-27, (2008).
[30] Timler, J., & Lent, C. S., “Power gain and dissipation in quantum-dot cellular automata. Journal of applied physics”, 91(2): 823-31, (2002).
[31] Srivastava, S., Asthana, A., Bhanja, S., & Sarkar, S., “QCAPro-an error-power estimation tool for QCA circuit design”, In 2011 IEEE international symposium of circuits and systems (ISCAS), IEEE, 2377-80, (2011).
[32] Taskin, B., & Hong, B., “Improving line-based QCA memory cell design through dual phase clocking”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(12): 1648-56, (2008).
[33] Taskin, B., Chiu, A., Salkind, J., & Venutolo, D., “A shift-register-based QCA memory architecture”, ACM Journal on Emerging Technologies in Computing Systems (JETC), 5(1): 4, (2009).
[34] Dehkordi, M. A., Shamsabadi, A. S., Ghahfarokhi, B. S., & Vafaei, A., “Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata”, Microelectronics Journal, 42(5): 701-08, (2011).
[35] Kianpour, M., & Sabbaghi-Nadooshan, R., “A novel design and simulation of 16 bits RAM implementation in quantum-dot cellular automata (QCA)”, In 2012 16th IEEE Mediterranean Electro technical Conference, IEEE, 637-40, (2012).
[36] Vankamamidi, V., Ottavi, M., & Lombardi, F., “A line-based parallel memory for QCA Implementation”, IEEE Transactions on Nanotechnology, 4(6): 690-98, (2005).
[37] Vankamamidi, V., Ottavi, M., & Lombardi, F., “A serial memory by quantum-dot cellular automata (QCA)”, IEEE Transactions on Computers, 57(5): 606-18, (2008).
[38] Berzon, D., & Fountain, T. J., “A memory design in QCAs using the SQUARES formalism”, In Proceedings Ninth Great Lakes Symposium on VLSI, IEEE, 166-69, (1999).
[39] Abdullah-Al-Shafi, M., Bahar, A. N., Ahmad, P. Z., Ahmad, F., Bhuiyan, M. M. R., & Ahmed, K., “Power analysis dataset for QCA based multiplexer circuits”. Data in Brief, 11: 593-96, (2017).
[40] Singh, G., “Design and performance analysis of a new efficient coplanar quantum-dot cellular automata adder”, Indian Journal of Pure & Applied Physics (IJPAP), 55(2): 97-103, (2017).