A Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

This study presents a Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized design has been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. The TRNG design has been synthesized and tested for the Virtex6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequencies of the TRNG in 32-bit IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard reach 344.585 MHz and 316 MHz, respectively. The throughputs of the TRNG in 32-bit IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard have been obtained as 344 Mbit/s and 316 Mbit/s, respectively. 1 Mbit sequence has been generated by using TRNG system. Randomness analysis of the generated numbers has been performed in accordance with the NIST 800-22 tests and the generated numbers have successfully passed all of the tests.

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