Hücre Başına Çoklu Bit Media Geliştirmek İçin Nano Ölçekli Yarı İletken Bir Aygıtın Sonlu Eleman Modellemesi

Genel olarak, temel bileşenler olarak kalkojen elementleri kullanan bir yarı iletken cihaz, gelecekteki ultra yüksek yoğunluklu veri depolama teknolojisi için potansiyel bir devrim teknolojisi olarak kabul edilmektedir. 0 ve 1 mantık durumları arasında yüksek kontrastlı bu tür cihazlar, veri depolama yoğunluğunu arttırmak için tek bir bitte birden çok mantık seviyesi fikrinin olası uygulaması olarak ortaya çıkmıştır. Mantık durumları arasındaki direnç seviyelerinin potansiyel stabilizasyonu, birkaç verinin tek bir hücrede (00, 01, 10, 11 seviyeleri gibi) depolanmasını sağlar. 3D sonlu eleman modelleme yoluyla hücre başına çoklu bit üretimi için nano ölçekli yarı iletken bir hücre içinde orta direnç durumlarının stabilize edilmesinde mevcut enjeksiyon ve malzeme seçiminin rolünün araştırıldığını rapor ediyorum. İlk olarak, anahtarlama dinamiklerinin karmaşık doğasını görselleştirmek için, faz değişimi kinetikleri, elektriksel, termal ve perkolasyon içeren iki aktif katman Ge2Sb2Te5 / Ge2Sb2Te5 (GST / GST) alaşımlı bir hücrede 3D sonlu eleman simülasyonları gerçekleştirildi. Simülasyon, sıcaklığın bir fonksiyonu olan birleştirilmiş diferansiyel denklemler ve termoelektrik etkiyi hesaba katmak için Seebeck katsayısı ile tekrarlamalı bir yaklaşım kullanılarak oluşturulmuştur. Anahtarlama dinamiklerinin karmaşık doğası, tam programlama voltajına ve malzeme özelliklerine karşı oldukça hassas görünmektedir. Model, dairesel üst temas cihazlarında beklenmedik bir şekilde kararlı orta durumların oluşumunun fiziksel kökeninin esas olarak bir programlama akımı darbesinin uygulanması sırasında anizotropik ısınmaya bağlı olduğunu göstermektedir. Model, gelecekteki ultra yüksek yoğunluklu veri depolama uygulamaları için bellek hücrelerini optimize etmek için kullanılabilecek bu tür karışık faz seviyeleri için gerekli programlama koşullarını ve malzeme seçimininin önemini başarıyla öngörmektedir.

Finite Element Modelling of a Nanoscale Semiconductor Device to Develop Multiple Bit per Cell Media

Generally, a semiconductor device using chalcogenide elements as a fundamental components is considered as a potentially revelationtechnology for future ultra-high density data storage technology. These kind of device having high contrast between 0 and 1 logic statesbrought out the possible application of the idea of multiple logic levels in a single bit in an effort to boost data storage density. Thepotential stabilization of resistance levels in between the logic states enables storage of several data in a single cell (such as 00, 01, 10, 11levels). I report on investigation of the role of the current injection and material selection in stabilizing middle resistance states within ananoscale semiconductor cell for fabrication of a multiple-bit-per-cell through 3D finite element modeling. First, to visualize the complexnature of the switching dynamics, 3D finite element simulations were carried out in cell with two active layers Ge2Sb2Te5/Ge2Sb2Te5(GST/GST) alloys incorporating phase change kinetics, electrical, thermal and percolation. Simulation was constructed by using aniterative approach with coupled differential equations, which are all as a function of temperature, as well as Seebeck coefficient to accountfor thermoelectric effect. The complex nature of switching dynamics appears highly sensitive to the exact programming voltage andmaterial properties. The model suggests that the physical origin of the formation of stable middle states unexpectedly in circular topcontact devices is mainly due to anisotropic heating during the application of a programming current pulse. The model successfullypredicts the required programing conditions and the importantce of material selection for such mixed-phase levels, which can be used tooptimize memory cells for future ultra-high-density data storage applications.

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