In this paper, a 2-D cylindrical gate tunnel FET (CG-TFET) model is developed based on the potential at the center of cylinder. The center potential is obtained by Laplace solution in the cylindrical coordinate system and the accuracy is validated using a 2-D TCAD device simulator. The tunneling of charge carriers in the CG-TFET is analyzed using the center potential and the results are compared to the surface potential-based model. The drain current is formulated using the initial tunneling point and tunneling path, which further helps to obtain the threshold voltage of this model. The effect of gate engineering and band-gap engineering on the drain current are investigated. The device scaling capability of the model is discussed extensively.